Using a dataflow abstracted virtual prototype for HdS-design
Proceedings of the 2009 Asia and South Pacific Design Automation Conference
On-the-fly hardware acceleration for protocol stack processing in next generation mobile devices
CODES+ISSS '09 Proceedings of the 7th IEEE/ACM international conference on Hardware/software codesign and system synthesis
Performance analysis of LTE protocol processing on an arm based mobile platform
SOC'09 Proceedings of the 11th international conference on System-on-chip
Virtual prototypes for software-dominated communication system designs
IEEE Communications Magazine
Joint Uplink and Downlink Performance Profiling of LTE Protocol Processing on a Mobile Platform
International Journal of Embedded and Real-Time Communication Systems
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Increasing system complexity not only in wireless communications forces design teams to avoid errors during the process of system refinement thereby keeping ambiguities during system implementation at a minimum. On the other hand the chosen system design approach has to ensure that a system design project rapidly advances through all stages of refinement from an algorithmic model to a real "System on Chip" (SoC) while maintaining backwards equivalence of the produced HW and FW/SW code with the original algorithmic model. This system design challenge also demands a new interdisciplinary team approach encompassing all design skills ranging from concept to HW and FW/SW engineering as well as system verification to increase the overlap in the system concept, implementation and verification phase. But how do these interdisciplinary teams cooperate efficiently, as they are used to metaphorically "speak different design languages"? Resulting in an industry record development time for a 3.5G UMTS modem the employment of a novel system design approach is shown which serves as common system design language, avoiding the babylonian language disaster of isolated engineering worlds. The motivation for an increasing overlap of system concept, implementation and verification phases is obvious: it can save time (to market) in the magnitude of several months or even more and thus drastically shorten design cycles by parallel development of HW and FW/SW. The proposed approach also helps to avoid costly redesign cycles due to conceptual errors and optimizes the quality of the developed system HW and FW/SW thereby also substantially reducing system development R&D costs.