Dynamic hardware/software partitioning: a first approach
Proceedings of the 40th annual Design Automation Conference
Efficient Modeling of Preemption in a Virtual Prototype
RSP '00 Proceedings of the 11th IEEE International Workshop on Rapid System Prototyping (RSP 2000)
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IPDPS '05 Proceedings of the 19th IEEE International Parallel and Distributed Processing Symposium (IPDPS'05) - Workshop 3 - Volume 04
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EURASIP Journal on Embedded Systems
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Proceedings of the First Workshop on Virtualization in Mobile Computing
On the Design of a Suitable Hardware Platform for Protocol Stack Processing in LTE Terminals
CSE '09 Proceedings of the 2009 International Conference on Computational Science and Engineering - Volume 02
Performance analysis of LTE protocol processing on an arm based mobile platform
SOC'09 Proceedings of the 11th international conference on System-on-chip
Implementation and benchmarking of hardware accelerators for ciphering in LTE terminals
GLOBECOM'09 Proceedings of the 28th IEEE conference on Global telecommunications
Joint Uplink and Downlink Performance Profiling of LTE Protocol Processing on a Mobile Platform
International Journal of Embedded and Real-Time Communication Systems
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In this paper we present a new on-the-fly hardware acceleration approach, based on a smart Direct Memory Access (sDMA) controller, for the layer 2 (L2) downlink protocol stack processing in Long Term Evolution (LTE) and beyond mobile devices. We use virtual prototyping in order to simulate an ARM1176 processor based hardware platform together with the executed software comprising an LTE protocol stack model. The sDMA controller with diff erent hardware accelerator units for the time critical algorithms in the protocol stack is implemented and integrated in the hardware platform. We prove our new hardware/software partitioning concept for the LTE L2 by measuring the average execution time per transport block in the protocol stack at di fferent activated on-the-fly hardware acceleration stages in the sDMA controller. At LTE data rates of 100 Mbit/s, we achieve a speedup of 24% compared to a pure software implementation by enabling the sDMA hardware support for header processing in the protocol stack. Furthermore, an activation of the complete on-the-fly hardware acceleration in the sDMA controller, including on-the-fly deciphering, leads to a speedup of more than 50 %. Finally, at transmission conditions with more computational demands and data rates up to 320 Mbit/s, we obtain acceleration ratios of almost 80 %. Investigations show that our new sDMA on-the-fly hardware acceleration approach in combination with a single-core processor off ers the required computational power for next generation mobile devices.