Analysis of Hardware Acceleration in Reconfigurable Embedded Systems

Authors:
Matthew Ouellette;Dan Connors
Affiliations:
Xilinx, Inc.;University of Colorado, Boulder
Venue:
IPDPS '05 Proceedings of the 19th IEEE International Parallel and Distributed Processing Symposium (IPDPS'05) - Workshop 3 - Volume 04
Year:
2005

Citing 1
Cited 3

Hardware/Software Codesign for FPGA-Based Systems

HICSS '99 Proceedings of the Thirty-Second Annual Hawaii International Conference on System Sciences-Volume 3 - Volume 3

Self-Reconfigurable Embedded Systems on Low-Cost FPGAs

IEEE Micro
On-the-fly hardware acceleration for protocol stack processing in next generation mobile devices

CODES+ISSS '09 Proceedings of the 7th IEEE/ACM international conference on Hardware/software codesign and system synthesis
Energy-efficient hardware architectures for the packet data convergence protocol in LTE-advanced mobile terminals

VLSI Design

Quantified Score

Hi-index	0.00

Visualization

Abstract

Embedded designers now have the capability of offloading software routines into custom application specific hardware blocks. This paper evaluates a domain-specific design system for configurable computing platforms that combine processors and configurable fabrics. Although the proposed work uses floating-point and communication primitives as the specific domain tasks evaluated, the reconfigurable computing platform and the design challenges addressed will become increasingly common in a number of embedded system environments. This paper explores the added cost of hardware resources, area, and power of moving software library routines into hardware blocks in a configurable embedded system based on the MicroBlaze soft processor.