Virtual synchronization for fast distributed cosimulation of dataflow task graphs
Proceedings of the 15th international symposium on System Synthesis
Multi-level software validation for NOC
Networks on chip
Virtual synchronization technique with OS modeling for fast and time-accurate cosimulation
Proceedings of the 1st IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
A Time Slice Based Scheduler Model for System Level Design
Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
A consistent design methodology for wireless embedded systems
EURASIP Journal on Applied Signal Processing
Efficient design methods for embedded communication systems
EURASIP Journal on Embedded Systems
On-the-fly hardware acceleration for protocol stack processing in next generation mobile devices
CODES+ISSS '09 Proceedings of the 7th IEEE/ACM international conference on Hardware/software codesign and system synthesis
Performance analysis of LTE protocol processing on an arm based mobile platform
SOC'09 Proceedings of the 11th international conference on System-on-chip
Joint Uplink and Downlink Performance Profiling of LTE Protocol Processing on a Mobile Platform
International Journal of Embedded and Real-Time Communication Systems
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A virtual prototype combines a hardware model with hardware/software cosimulation to support the development and debugging of embedded software before a hardware prototype is available. Existing techniques for hardware/software cosimulation execute the software either on an instruction set simulator for accuracy, or on the simulator host processor for increased performance.On the host processor, timing is either completely ignored or approximated using timing annotations in the code. Although preemption (interrupts) can strongly influence the timing, it is rarely modeled to avoid a performance degrading that would make the virtual prototype unusable, especially for real time signal processing software simulations which is already time consuming as such.We propose a technique to accurately model preemption and its effect on software timing in a simulation based on host code execution. Our technique has been implemented in the TIPSY \CPP/ library for executable system modeling; pseudo C-code for this implementation with several optimizations is included in this paper. With this implementation, a preemptive scheduler model can easily be created or taken from a library and inserted in a system model without changing the original code to observe the effect of preemption on the system behavior.