DAC '96 Proceedings of the 33rd annual Design Automation Conference
Fast hardware/software co-simulation for virtual prototyping and trade-off analysis
DAC '97 Proceedings of the 34th annual Design Automation Conference
Optimistic distributed timed cosimulation based on thread simulation model
Proceedings of the 6th international workshop on Hardware/software codesign
Virtual synchronization for fast distributed cosimulation of dataflow task graphs
Proceedings of the 15th international symposium on System Synthesis
Efficient Modeling of Preemption in a Virtual Prototype
RSP '00 Proceedings of the 11th IEEE International Workshop on Rapid System Prototyping (RSP 2000)
Automatic Generation of Fast Timed Simulation Models for Operating Systems in SoC Design
Proceedings of the conference on Design, automation and test in Europe
RTOS-centric hardware/software cosimulator for embedded system design
Proceedings of the 2nd IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
Virtual Hardware Prototyping through Timed Hardware-Software Co-Simulation
Proceedings of the conference on Design, Automation and Test in Europe - Volume 2
Scheduling refinement in abstract RTOS models
ACM Transactions on Embedded Computing Systems (TECS)
Interrupt modeling for efficient high-level scheduler design space exploration
ACM Transactions on Design Automation of Electronic Systems (TODAES)
CODES+ISSS '08 Proceedings of the 6th IEEE/ACM/IFIP international conference on Hardware/Software codesign and system synthesis
Integration, the VLSI Journal
A cosimulation methodology for HW/SW validation and performance estimation
ACM Transactions on Design Automation of Electronic Systems (TODAES)
An Extended SystemC Framework for Efficient HW/SW Co-Simulation
ACM Transactions on Design Automation of Electronic Systems (TODAES)
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Hardware/Software cosimulation is the key process to shorten the design turn around time. We have proposed a novel technique, called virtual synchronization, for fast and time accurate cosimulation that involves interacting component simulators. In this paper, we further extend the virtual synchronization technique with OS modeling for the case where multiple software tasks are executed under the supervision of a real-time operating system. The OS modeler models the RTOS overheads of context switching and tick interrupt handling as well as preemption behavior. While maintaining the timing accuracy to an acceptable level below a few percents, we could reduce the simulation time drastically compared with existent conservative approach by removing the need of time synchronization between simulators. It is confirmed with a preliminary experiment with a multimedia example that consists of four real-life tasks.