A hardware-software co-simulator for embedded system design and debugging
ASP-DAC '95 Proceedings of the 1995 Asia and South Pacific Design Automation Conference
Hardware-software co-design of embedded systems: the POLIS approach
Hardware-software co-design of embedded systems: the POLIS approach
Software timing analysis using HW/SW cosimulation and instruction set simulator
Proceedings of the 6th international workshop on Hardware/software codesign
Multilanguage design of heterogeneous systems
CODES '99 Proceedings of the seventh international workshop on Hardware/software codesign
Proceedings of the 37th Annual Design Automation Conference
Optimized timed hardware software cosimulation without roll-back
Proceedings of the conference on Design, automation and test in Europe
Methodology for hardware/software co-verification in C/C++ (short paper)
ASP-DAC '00 Proceedings of the 2000 Asia and South Pacific Design Automation Conference
Virtual synchronization for fast distributed cosimulation of dataflow task graphs
Proceedings of the 15th international symposium on System Synthesis
System-on-a-Chip Cosimulation and Compilation
IEEE Design & Test
Fast Timed Cosimulation of HW/SW Implementation of Embedded Multiprocessor SoC Communication
HLDVT '01 Proceedings of the Sixth IEEE International High-Level Design Validation and Test Workshop (HLDVT'01)
Virtual synchronization technique with OS modeling for fast and time-accurate cosimulation
Proceedings of the 1st IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
Native ISS-SystemC Integration for the Co-Simulation of Multi-Processor SoC
Proceedings of the conference on Design, automation and test in Europe - Volume 1
A timing-accurate HW/SW co-simulation of an ISS with SystemC
Proceedings of the 2nd IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
Timed HW-SW cosimulation using native execution of OS and application SW
HLDVT '02 Proceedings of the Seventh IEEE International High-Level Design Validation and Test Workshop
TRAIN: a virtual transaction layer architecture for TLM-based HW/SW codesign of synthesizable MPSoC
Proceedings of the conference on Design, automation and test in Europe: Proceedings
Modeling and simulation alternatives for the design of networked embedded systems
Proceedings of the conference on Design, automation and test in Europe
A non-intrusive timing synchronization interface for hardware-assisted HW/SW co-simulation
Proceedings of the 49th Annual Design Automation Conference
| Hi-index | 0.00 |
Designers of factory automation applications increasingly demand for tools for rapid prototyping of hardware extensions to existing systems and verification of resulting behaviors through hardware and software co-simulation. This work presents a framework for the timing-accurate co-simulation of HDL models and their verification against hardware and software running on an actual embedded device of which only a minimal knowledge of the current design is required. Experiments on real-life applications show that early architectural and design decisions can be taken by measuring the expected performance on the models realized using the proposed framework.