Hardware-software co-design of embedded systems: the POLIS approach
Hardware-software co-design of embedded systems: the POLIS approach
Software timing analysis using HW/SW cosimulation and instruction set simulator
Proceedings of the 6th international workshop on Hardware/software codesign
Multilanguage design of heterogeneous systems
CODES '99 Proceedings of the seventh international workshop on Hardware/software codesign
Proceedings of the 37th Annual Design Automation Conference
Methodology for hardware/software co-verification in C/C++ (short paper)
ASP-DAC '00 Proceedings of the 2000 Asia and South Pacific Design Automation Conference
System-on-a-Chip Cosimulation and Compilation
IEEE Design & Test
Native ISS-SystemC Integration for the Co-Simulation of Multi-Processor SoC
Proceedings of the conference on Design, automation and test in Europe - Volume 1
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Exploring SW Performance Using SoC Transaction-Level Modeling
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe: Designers' Forum - Volume 2
Estimation of Bus Performance for a Tuplespace in an Embedded Architecture
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe: Designers' Forum - Volume 2
Timed HW-SW cosimulation using native execution of OS and application SW
HLDVT '02 Proceedings of the Seventh IEEE International High-Level Design Validation and Test Workshop
Virtual Hardware Prototyping through Timed Hardware-Software Co-Simulation
Proceedings of the conference on Design, Automation and Test in Europe - Volume 2
High-level architecture exploration for MPEG4 encoder with custom parameters
ASP-DAC '06 Proceedings of the 2006 Asia and South Pacific Design Automation Conference
Software-friendly HW/SW co-simulation: an industrial case study
Proceedings of the conference on Design, automation and test in Europe: Designers' forum
SciSim: a software performance estimation framework using source code instrumentation
WOSP '08 Proceedings of the 7th international workshop on Software and performance
CODES+ISSS '08 Proceedings of the 6th IEEE/ACM/IFIP international conference on Hardware/Software codesign and system synthesis
MC-Sim: an efficient simulation tool for MPSoC designs
Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design
ARCS'10 Proceedings of the 23rd international conference on Architecture of Computing Systems
A non-intrusive timing synchronization interface for hardware-assisted HW/SW co-simulation
Proceedings of the 49th Annual Design Automation Conference
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The paper presents a system level co-simulation methodology for modeling, validating, and analyzing the performance of embedded systems. The proposed solution relies on the integration between an instruction set simulator (ISS) and the SystemC simulation kernel. In this way, the ISS is used to abstract the model of the real programmable device where the SW should run, while SystemC is used to model HW components that interact with the SW. A correct validation of such an architecture is infeasible without taking care of timing information. Thus, the paper proposes an effective timing synchronization mechanism, which uses timing information of an ISS (or a board) to synchronize the SystemC simulation.