Image and Video Compression Standards: Algorithms and Architectures
Image and Video Compression Standards: Algorithms and Architectures
A complexity effective communication model for behavioral modeling of signal processing applications
Proceedings of the 40th annual Design Automation Conference
Specification, Modeling and Design Tools for System-on-Chip
ASP-DAC '02 Proceedings of the 2002 Asia and South Pacific Design Automation Conference
Proceedings of the 41st annual Design Automation Conference
Debugging HW/SW interface for MPSoC: video encoder system design case study
Proceedings of the 41st annual Design Automation Conference
Proceedings of the 2nd IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
A timing-accurate HW/SW co-simulation of an ISS with SystemC
Proceedings of the 2nd IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
Design and programming of embedded multiprocessors: an interface-centric approach
Proceedings of the 2nd IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
High-level heterogeneous distributed parallel programming
ISICT '04 Proceedings of the 2004 international symposium on Information and communication technologies
A software-based MPEG-4 video encoder using parallel processing
IEEE Transactions on Circuits and Systems for Video Technology
Parallelization methodology for video coding-an implementation on the TMS320C80
IEEE Transactions on Circuits and Systems for Video Technology
Design space exploration of IEEE 802.11n using SystemC
IMCAS'07 Proceedings of the 6th WSEAS International Conference on Instrumentation, Measurement, Circuits and Systems
Architecture level simulation of IEEE 802.11N MAC using SystemC
AsiaCSN '08 Proceedings of the Fifth IASTED International Conference on Communication Systems and Networks
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this paper proposes the use of a high-level architecture exploration method for different MPEG4 video encoders using different customization parameters. The targeted architecture is a heterogeneous MP-SoC which may include up 2 coarse grain SIMD (task level SIMD) subsystems to perform the computations. The customization parameters are related to video resolution, frame rate, Communication Network, level of parallelism and CPU types. These parameters are determined during the high-level architecture exploration, by estimating the architecture performances at early stages of the design flow. Experiments shows that the error factor of these high-level performances estimations are less than 10% compared to those obtained with final manually implemented RTL architecture. This method was used successfully for exploration of different MPEG4 architecture configurations with different customization parameters. We consider these experiments a break-through because they show how a complex design can be mastered through a set of pragmatic choices.