High-level architecture exploration for MPEG4 encoder with custom parameters
ASP-DAC '06 Proceedings of the 2006 Asia and South Pacific Design Automation Conference
Methodology of High-Level Transaction Level Modeling Using 802.11 PHY Example
IEICE - Transactions on Information and Systems
Integrated System-Level Modeling of Network-on-Chip enabled Multi-Processor Platforms
Integrated System-Level Modeling of Network-on-Chip enabled Multi-Processor Platforms
Transaction-Level Modeling with Systemc: Tlm Concepts and Applications for Embedded Systems
Transaction-Level Modeling with Systemc: Tlm Concepts and Applications for Embedded Systems
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This paper proposes a method to simulate the system architecture of IEEE 802.11n MAC. Transaction level modeling(TLM) of bus based SoC platform is used as design approach. Various architectural options such as processor and bus clock speeds, memory response time, and memory size are evaluated with application specific performance metrics. The architecture is verified using the real-time constraints of IEEE 802.11n. In addition, further architecture analysis is performed to evaluate performance metrics in terms of the average and instantaneous throughput.