Hardware/software co-simulation in a VHDL-based test bench approach
DAC '97 Proceedings of the 34th annual Design Automation Conference
A Model and Methodology for Hardware-Software Codesign
IEEE Design & Test
Computer-Aided Hardware-Software Codesign
IEEE Micro
A timing-accurate HW/SW co-simulation of an ISS with SystemC
Proceedings of the 2nd IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
RTOS-centric hardware/software cosimulator for embedded system design
Proceedings of the 2nd IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
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This paper proposes a novel HW/SW co-simulation approach that minimizes the impact on software designers. We propose a SystemC-based system that enables the software team to test their software with their own tools and environment using an accurate simulated ASIC (Application Specific Integrated Circuit) model.The solution presented here enables a smooth and early ASIC and SW integration, which reduces the project development time and improves the ASIC design quality (i.e., SW engineers can help in the ASIC verification and ASIC engineers can help in the SW development). In this solution, the real and full software (i.e., multi-threaded application) runs in its native environment with minimal changes and interfaces with a simulated ASIC model using sockets. We have tested this approach on a pilot-project, which has demonstrated the feasibility of this co-development methodology.