A SystemC Refinement Methodology for Embedded Software
IEEE Design & Test
Proceedings of the conference on Design, automation and test in Europe: Proceedings
Proceedings of the conference on Design, automation and test in Europe: Proceedings
Performance guarantees by simulation of process
SCOPES '05 Proceedings of the 2005 workshop on Software and compilers for embedded systems
A high-level requirements engineering methodology for electronic system-level design
Computers and Electrical Engineering
Proceedings of the conference on Design, automation and test in Europe
Journal of Signal Processing Systems
SDL/virtual prototype co-design for rapid architectural exploration of a mobile phone platform
SDL'09 Proceedings of the 14th international SDL conference on Design for motes and mobiles
Hardware design and simulation for verification
SFM'06 Proceedings of the 6th international conference on Formal Methods for the Design of Computer, Communication, and Software Systems
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Transaction-level models (TLMs) address the problems of designing increasingly complex systems by raising the level of design abstraction above RTL. However, TLM terminology is presently a subject of contentious debate and a coherent set of TLM use-models have not been proposed. In this paper we propose a variety of TLM use-models that reveal paths through the TLM abstraction levels for various types of system. We begin by stating the abstraction levels that comprise ýtransaction-levelý and identify roles and responsibilities that apply within the use-models. We then take each use-model and discuss the type of system it applies to, the TLM abstraction levels it supports, and the design activites applied at those levels. We also consider the distribution of modeling effort between the various design rôles and apply that to descriptions of various use-model design flows.