DAC '97 Proceedings of the 34th annual Design Automation Conference
System Design with SystemC
Transaction level modeling: an overview
Proceedings of the 1st IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
Proceedings of the conference on Design, automation and test in Europe - Volume 3
System design for DSP applications in transaction level modeling paradigm
Proceedings of the 41st annual Design Automation Conference
Synchronization Processor Synthesis for Latency Insensitive Systems
Proceedings of the conference on Design, Automation and Test in Europe - Volume 2
Transaction Level Modeling: Flows and Use Models
CODES+ISSS '04 Proceedings of the international conference on Hardware/Software Codesign and System Synthesis: 2004
A formal method for hardware IP design and integration under I/O and timing constraints
ACM Transactions on Embedded Computing Systems (TECS)
A Computation Core for Communication Refinement of Digital Signal Processing Algorithms
DSD '06 Proceedings of the 9th EUROMICRO Conference on Digital System Design
Transaction-Level Modeling with Systemc: Tlm Concepts and Applications for Embedded Systems
Transaction-Level Modeling with Systemc: Tlm Concepts and Applications for Embedded Systems
A framework for comparing models of computation
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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Early exploration of communication architectures and timing behaviors is a key step in modern system design flows. This paper proposes a framework for the design space exploration of DSP applications. The proposed approach is based on four main abstraction levels: algorithmic, architectural (communication interface), behavioral (I/O timing diagram) and RTL. The system specification is based on a set of Behavioral Description Models (BDM) which communicate through channels: each BDM represents a hardware component. For this purpose, a BDM (1) embeds a sequential function--that describes the computing algorithm to be implemented--into a module and (2) includes a set of I/O and control processes. Communication architectures and timing behaviors (I/O scheduling, I/O parallelism...) of each BDM can be modified and easily explored by adding I/O and control code into the dedicated concurrent processes. This allows keeping the description of the functionality unchanged throughout the refinement steps. The high-level synthesis tool GAUT is next used to generate, from the unmodified sequential function, the RTL architectures that respect the constraints i.e. the refined I/O timing behavior. The use of BDMs for the system description allows the designer to simulate and to evaluate several communication architectures and several timing behaviors during the performance analysis phase. The interest of our approach is shown through the case study of a Hyper-plane Intersection and Selection HIS algorithm for MC-CDMA system.