Transaction Level Modeling: Flows and Use Models
CODES+ISSS '04 Proceedings of the international conference on Hardware/Software Codesign and System Synthesis: 2004
Exploiting TLM and object introspection for system-level simulation
Proceedings of the conference on Design, automation and test in Europe: Proceedings
Automatic Generation of Schedulings for Improving the Test Coverage of Systems-on-a-Chip
FMCAD '06 Proceedings of the Formal Methods in Computer Aided Design
Transaction-Level Modeling with Systemc: Tlm Concepts and Applications for Embedded Systems
Transaction-Level Modeling with Systemc: Tlm Concepts and Applications for Embedded Systems
Partial order method for timed simulation of system-level MPSoC designs
Proceedings of the 2009 Asia and South Pacific Design Automation Conference
Contract-Based Coordination of Hardware Components for the Development of Embedded Software
COORDINATION '09 Proceedings of the 11th International Conference on Coordination Models and Languages
Formal and executable contracts for transaction-level modeling in SystemC
EMSOFT '09 Proceedings of the seventh ACM international conference on Embedded software
A fast and effective dynamic trace-based method for analyzing architectural performance
Proceedings of the 16th Asia and South Pacific Design Automation Conference
Proceedings of the eighth IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
Fast and accurate TLM simulations using temporal decoupling for FIFO-based communications
Proceedings of the Conference on Design, Automation and Test in Europe
System-level modeling of energy in TLM for early validation of power and thermal management
Proceedings of the Conference on Design, Automation and Test in Europe
| Hi-index | 0.00 |
Transaction Level Modeling (TLM) captures abstract models of Systems-on-Chip that simulate faster than traditional RTL simulations and are available earlier in the design flow. Such models allow the development of the embedded software on a virtual prototype of the hardware, before the chip is available. Various levels of details in TL models are needed; using untimed and timed models for different purposes is a usual practice. We present a method for developing very abstract untimed models first, and then enriching them to get detailed timed models, while preserving the functionality. The timed models can be as rich as the models usually written from scratch. The experiments with industrial case-studies show improved simulation speed and reduced modeling effort for both untimed and timed models.