ACM Transactions on Programming Languages and Systems (TOPLAS)
Circular scheduling: a new technique to perform software pipelining
PLDI '91 Proceedings of the ACM SIGPLAN 1991 conference on Programming language design and implementation
Computer architecture (2nd ed.): a quantitative approach
Computer architecture (2nd ed.): a quantitative approach
Asynchronous distributed simulation via a sequence of parallel computations
Communications of the ACM - Special issue on simulation modeling and statistical computing
System Design: A Practical Guide with Specc
System Design: A Practical Guide with Specc
A New Optimized Implemention of the SystemC Engine Using Acyclic Scheduling
Proceedings of the conference on Design, automation and test in Europe - Volume 1
An integrated hardware/software approach for run-time scratchpad management
Proceedings of the 41st annual Design Automation Conference
MPARM: Exploring the Multi-Processor SoC Design Space with SystemC
Journal of VLSI Signal Processing Systems
Exploiting coarse-grained task, data, and pipeline parallelism in stream programs
Proceedings of the 12th international conference on Architectural support for programming languages and operating systems
Proceedings of the conference on Design, automation and test in Europe
Introducing preemptive scheduling in abstract RTOS models using result oriented modeling
Proceedings of the conference on Design, automation and test in Europe
Framework for fast and accurate performance simulation of multiprocessor systems
HLDVT '07 Proceedings of the 2007 IEEE International High Level Design Validation and Test Workshop
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Current discrete event simulator requires heavy simulation overhead to switch between different components to simulate them in strictly chronological order. Therefore, timed simulation is significantly slower than un-timed simulation. By simply adding delays in the components and communication channels, our timed MPEG-2 decoder simulates more than 14 times slower than an un-timed simulation. In this paper, we propose a partial order method to speed up timed simulation by relaxing the order that the components are simulated. With partial order method, a component is not required to schedule a channel access if both behavioral and timing results of the access are known. The simulation switches less frequently hence the simulation overhead reduces. We show that partial order method can be used in complex system-level simulation such as MPSoC implementations of the MPEG-2 decoder. In our experiments, partial order method provides more than 10 times speedups over regular discrete event simulation for timed simulation.