System-level power estimation and optimization
ISLPED '98 Proceedings of the 1998 international symposium on Low power electronics and design
State-based power analysis for systems-on-chip
Proceedings of the 40th annual Design Automation Conference
Accurate temperature-dependent integrated circuit leakage power estimation is easy
Proceedings of the conference on Design, automation and test in Europe
Accurate and fast system-level power modeling: An XScale-based case study
ACM Transactions on Embedded Computing Systems (TECS)
Proceedings of the conference on Design, automation and test in Europe
Power Modeling in SystemC at Transaction Level, Application to a DVFS Architecture
ISVLSI '08 Proceedings of the 2008 IEEE Computer Society Annual Symposium on VLSI
Thermal analysis of multiprocessor SoC applications by simulation and verification
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Hotspot: acompact thermal modeling methodology for early-stage VLSI design
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
System-level power and timing variability characterization to compute thermal guarantees
CODES+ISSS '11 Proceedings of the seventh IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
ESL solutions for low power design
Proceedings of the International Conference on Computer-Aided Design
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Modern systems-on-a-chip are equipped with power architectures, allowing to control the consumption of individual components or subsystems. These mechanisms are controlled by a power-management policy often implemented in the embedded software, with hardware support. Today's circuits have an important static power consumption, whose low-power design require techniques like DVFS or power-gating. A correct and efficient management of these mechanisms is therefore becoming non-trivial. Validating the effect of the power management policy needs to be done very early in the design cycle, as part of the architecture exploration activity. High-level models of the hardware must be annotated with consumption information. Temperature must also be taken into account since leakage current increases exponentially with it. Existing annotation techniques applied to loosely-timed or temporally-decoupled models would create bad simulation artifacts on the temperature profile (e.g. unrealistic peaks). This paper addresses the instrumentation of a timed transaction-level model of the hardware with information on the power consumption of the individual components. It can cope not only with power-state models, but also with Joule-per-bit traffic models, and avoids simulation artifacts when used in a functional/power/temperature co-simulation.