Proceedings of the conference on Design, automation and test in Europe: Proceedings
A framework for embedded system specification under different models of computation in SystemC
Proceedings of the 43rd annual Design Automation Conference
Automatic Generation of Schedulings for Improving the Test Coverage of Systems-on-a-Chip
FMCAD '06 Proceedings of the Formal Methods in Computer Aided Design
Proceedings of the conference on Design, automation and test in Europe
Parallel simulation of SystemC TLM 2.0 compliant MPSoC on SMP workstations
Proceedings of the Conference on Design, Automation and Test in Europe
DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
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A known approach to improve the timing accuracy of an untimed or loosely timed TLM model is to add timing annotations into the code and to reduce the number of costly context switches using temporal decoupling, meaning that a process can go ahead of the simulation time before synchronizing again. Our current goal is to apply temporal decoupling to the TLM platform of a heterogeneous many-core SoC dedicated to high performance computing. Part of this SoC communicates using classic memory-mapped buses, but it can be extended with hardware accelerators communicating using FIFOs. Whereas temporal decoupling for memory-based transactions has been widely studied, FIFO-based communications raise issues that have not been addressed before. In this paper, we provide an efficient solution to combine temporal decoupling and FIFO-based communications.