UNIX systems for modern architectures: symmetric multiprocessing and caching for kernel programmers
UNIX systems for modern architectures: symmetric multiprocessing and caching for kernel programmers
Threads primer: a guide to multithreaded programming
Threads primer: a guide to multithreaded programming
Expanding Symmetric Multiprocessor Capability Through Gang Scheduling
IPPS/SPDP '98 Proceedings of the Workshop on Job Scheduling Strategies for Parallel Processing
Proceedings of the conference on Design, automation and test in Europe: Proceedings
Distributed Simulation: A Case Study in Design and Verification of Distributed Programs
IEEE Transactions on Software Engineering
Operating Systems: Internals and Design Principles
Operating Systems: Internals and Design Principles
HLA-based simulation environment for distributed SystemC simulation
Proceedings of the 4th International ICST Conference on Simulation Tools and Techniques
On the automatic synthesis of parallel SW from RTL models of hardware IPs
Proceedings of the great lakes symposium on VLSI
SystemC simulation on GP-GPUs: CUDA vs. OpenCL
Proceedings of the eighth IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
Parallel programming with SystemC for loosely timed models: a non-intrusive approach
Proceedings of the Conference on Design, Automation and Test in Europe
Fast and accurate TLM simulations using temporal decoupling for FIFO-based communications
Proceedings of the Conference on Design, Automation and Test in Europe
On the use of GP-GPUs for accelerating compute-intensive EDA applications
Proceedings of the Conference on Design, Automation and Test in Europe
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The simulation speed is a key issue in virtual prototyping of Multi-Processors System on Chip (MPSoCs). The SystemC TLM2.0 (Transaction Level Modeling) approach accelerates the simulation by using Interface Method Calls (IMC) to implement the communications between hardware components. Another source of speedup can be exploited by parallel simulation. Multi-core workstations are becoming the mainstream, and SMP workstations will soon contain several tens of cores. The standard SystemC simulation engine uses a centralized scheduler, that is clearly the bottleneck for a parallel simulation. This paper has two main contributions. The first is a general modeling strategy for shared memory MPSoCs, called TLM-DT (Transaction Level Modeling with Distributed Time). The second is a truly parallel simulation engine, called SystemC-SMP. First experimental results on a 40 processor MPSoC virtual prototype running on a dual-core workstation demonstrate a 1.8 speedup, versus a sequential simulation.