Verification of Transaction-Level SystemC models using RTL Testbenches
MEMOCODE '03 Proceedings of the First ACM and IEEE International Conference on Formal Methods and Models for Co-Design
Transaction level modeling: an overview
Proceedings of the 1st IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
Proceedings of the conference on Design, automation and test in Europe: Proceedings
Hybrid, Incremental Assertion-Based Verification for TLM Design Flows
IEEE Design & Test
Relaxing Synchronization in a Parallel SystemC Kernel
ISPA '08 Proceedings of the 2008 IEEE International Symposium on Parallel and Distributed Processing with Applications
Parallelizing SystemC Kernel for Fast Hardware Simulation on SMP Machines
PADS '09 Proceedings of the 2009 ACM/IEEE/SCS 23rd Workshop on Principles of Advanced and Distributed Simulation
A Parallel SystemC Environment: ArchSC
ICPADS '09 Proceedings of the 2009 15th International Conference on Parallel and Distributed Systems
Parallel simulation of SystemC TLM 2.0 compliant MPSoC on SMP workstations
Proceedings of the Conference on Design, Automation and Test in Europe
SCGPSim: a fast SystemC simulator on GPUs
Proceedings of the 2010 Asia and South Pacific Design Automation Conference
A Comprehensive Performance Comparison of CUDA and OpenCL
ICPP '11 Proceedings of the 2011 International Conference on Parallel Processing
SAGA: SystemC acceleration on GPU architectures
Proceedings of the 49th Annual Design Automation Conference
On the use of GP-GPUs for accelerating compute-intensive EDA applications
Proceedings of the Conference on Design, Automation and Test in Europe
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SystemC is a widespread language for developing SoC designs. Unfortunately, most SystemC simulators are based on a strictly sequential scheduler that heavily limits their performance, impacting verification schedules and time-to-market of new designs. Parallelizing SystemC simulation entails a complete re-design of the simulator kernel for the specific target parallel architectures. This paper proposes an automatic methodology to generate a parallel SystemC simulator kernel, exploiting the massive parallelism of GP-GPU architectures. Our solution leverages static scheduling to reduce synchronization overheads. The generated simulator code targets both CUDA and OpenCL libraries, to boost scalability and provide support for multiple GP-GPU architectures. Finally, the paper compares the performance of our solution on CUDA vs. OpenCL platforms, with the goal of investigating advantages and drawbacks that the two thread management libraries offer to concurrent SystemC simulation.