Online SystemC emulation acceleration
Proceedings of the 47th Design Automation Conference
parSC: synchronous parallel systemc simulation on multi-core host architectures
CODES/ISSS '10 Proceedings of the eighth IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
Accelerating UNISIM-Based Cycle-Level Microarchitectural Simulations on Multicore Platforms
ACM Transactions on Design Automation of Electronic Systems (TODAES)
HLA-based simulation environment for distributed SystemC simulation
Proceedings of the 4th International ICST Conference on Simulation Tools and Techniques
SAGA: SystemC acceleration on GPU architectures
Proceedings of the 49th Annual Design Automation Conference
A Framework for exploration of parallel SystemC simulation on the single-chip cloud computer
Proceedings of the 5th International ICST Conference on Simulation Tools and Techniques
SystemC simulation on GP-GPUs: CUDA vs. OpenCL
Proceedings of the eighth IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
Parallel programming with SystemC for loosely timed models: a non-intrusive approach
Proceedings of the Conference on Design, Automation and Test in Europe
On the use of GP-GPUs for accelerating compute-intensive EDA applications
Proceedings of the Conference on Design, Automation and Test in Europe
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SystemC has become a very popular standardized language for the modeling of System-On-Chip (SoC) devices. However, due to the ever increasing complexity of SoC designs, the ever longer simulation times affect SoC exploration potential and time-to-market. In order to reduce these times, we have developed a parallel SystemC kernel. Because the SystemC semantics require a high level of synchronization which can dramatically affect the performance gains, we investigate in this paper some ways to reduce the synchronization overheads. We validate then our approaches against an academic design model and a real, industrial application.