parSC: synchronous parallel systemc simulation on multi-core host architectures

  • Authors:
  • Christoph Schumacher;Rainer Leupers;Dietmar Petras;Andreas Hoffmann

  • Affiliations:
  • RWTH Aachen University, Aachen, Germany;RWTH Aachen University, Aachen, Germany;Synopsys, Inc., Aachen, Germany;Synopsys, Inc., Aachen, Germany

  • Venue:
  • CODES/ISSS '10 Proceedings of the eighth IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
  • Year:
  • 2010

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Abstract

Time-consuming cycle-accurate MPSoC simulation is often needed for debugging and verification. Its practicability is put at risk by the growing MPSoC complexity. This work presents a conservative synchronous parallel simulation approach along with a SystemC framework to accelerate tightly-coupled MPSoC simulations on multi-core hosts. Key contribution is the implementation strategy, which utilizes techniques from the high-performance computing domain. Results show speed-ups of up to 4.4 on four host cores.