Parallel discrete event simulation
Communications of the ACM - Special issue on simulation
Parallel execution for serial simulators
ACM Transactions on Modeling and Computer Simulation (TOMACS)
System Design with SystemC
Distributed Simulation: A Case Study in Design and Verification of Distributed Programs
IEEE Transactions on Software Engineering
System-on-chip environment: a SpecC-based framework for heterogeneous MPSoC design
EURASIP Journal on Embedded Systems - C-Based Design of Heterogeneous Embedded Systems
Parallelizing SystemC Kernel for Fast Hardware Simulation on SMP Machines
PADS '09 Proceedings of the 2009 ACM/IEEE/SCS 23rd Workshop on Principles of Advanced and Distributed Simulation
parSC: synchronous parallel systemc simulation on multi-core host architectures
CODES/ISSS '10 Proceedings of the eighth IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
Multi-core parallel simulation of system-level description languages
Proceedings of the 16th Asia and South Pacific Design Automation Conference
Multicore Simulation of Transaction-Level Models Using the SoC Environment
IEEE Design & Test
A conservative approach to systemc parallelization
ICCS'06 Proceedings of the 6th international conference on Computational Science - Volume Part IV
Overview of the H.264/AVC video coding standard
IEEE Transactions on Circuits and Systems for Video Technology
Optimized out-of-order parallel discrete event simulation using predictions
Proceedings of the Conference on Design, Automation and Test in Europe
Parallel programming with SystemC for loosely timed models: a non-intrusive approach
Proceedings of the Conference on Design, Automation and Test in Europe
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At the Electronic System Level (ESL), design validation often relies on discrete event (DE) simulation. Recently, parallel simulators have been proposed which increase simulation speed by using multiple cores available on today's PCs. However, the total order of time in DE simulation is a bottleneck that severely limits the benefits of parallel simulation. This paper presents a new out-of-order simulator for multi-core parallel DE simulation of hardware/software designs at any abstraction level. By localizing the simulation time and carefully handling events at different times, a system model can be simulated following a partial order of time. Subject to automatic static data analysis at compile time and table-based decisions at run time, threads can be issued early which reduces the idle time of available cores. Our experiments show high performance gains in simulation speed with only a small increase of compile time.