Relaxing Synchronization in a Parallel SystemC Kernel
ISPA '08 Proceedings of the 2008 IEEE International Symposium on Parallel and Distributed Processing with Applications
Parallelizing SystemC Kernel for Fast Hardware Simulation on SMP Machines
PADS '09 Proceedings of the 2009 ACM/IEEE/SCS 23rd Workshop on Principles of Advanced and Distributed Simulation
Race analysis for systemc using model checking
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Parallel simulation of SystemC TLM 2.0 compliant MPSoC on SMP workstations
Proceedings of the Conference on Design, Automation and Test in Europe
parSC: synchronous parallel systemc simulation on multi-core host architectures
CODES/ISSS '10 Proceedings of the eighth IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
Multi-core parallel simulation of system-level description languages
Proceedings of the 16th Asia and South Pacific Design Automation Conference
A conservative approach to systemc parallelization
ICCS'06 Proceedings of the 6th international conference on Computational Science - Volume Part IV
Out-of-order parallel simulation for ESL design
DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
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The SystemC/TLM technologies are widely accepted in the industry for fast system-level simulation. An important limitation of SystemC regarding performance is that the reference implementation is sequential, and the official semantics makes parallel executions difficult. As the number of cores in computers increase quickly, the ability to take advantage of the host parallelism during a simulation is becoming a major concern. Most existing work on parallelization of SystemC targets cycle-accurate simulation, and would be inefficient on loosely timed systems since they cannot run in parallel processes that do not execute simultaneously. We propose an approach that explicitly targets loosely timed systems, and offers the user a set of primitives to express tasks with duration, as opposed to the notion of time in SystemC which allows only instantaneous computations and time elapses without computation. Our tool exploits this notion of duration to run the simulation in parallel. It runs on top of any (unmodified) SystemC implementation, which lets legacy SystemC code continue running as-it-is. This allows the user to focus on the performance-critical parts of the program that need to be parallelized.