COSMOS: a compiled simulator for MOS circuits
DAC '87 Proceedings of the 24th ACM/IEEE Design Automation Conference
High performance parallel logic simulations on a network of workstations
PADS '93 Proceedings of the seventh workshop on Parallel and distributed simulation
Parallel Logic Simulation Using Time Warp on Shared-Memory Multiprocessors
Proceedings of the 8th International Symposium on Parallel Processing
Optimizing system models for simulation efficiency
Formal methods and models for system design
Speeding up SystemC simulation through process splitting
Proceedings of the conference on Design, automation and test in Europe
Proceedings of the conference on Design, automation and test in Europe
Relaxing Synchronization in a Parallel SystemC Kernel
ISPA '08 Proceedings of the 2008 IEEE International Symposium on Parallel and Distributed Processing with Applications
Parallelizing SystemC Kernel for Fast Hardware Simulation on SMP Machines
PADS '09 Proceedings of the 2009 ACM/IEEE/SCS 23rd Workshop on Principles of Advanced and Distributed Simulation
Event-driven gate-level simulation with GP-GPUs
Proceedings of the 46th Annual Design Automation Conference
Parallel Cycle Based Logic Simulation Using Graphics Processing Units
ISPDC '10 Proceedings of the 2010 Ninth International Symposium on Parallel and Distributed Computing
Parallel simulation of SystemC TLM 2.0 compliant MPSoC on SMP workstations
Proceedings of the Conference on Design, Automation and Test in Europe
GCS: high-performance gate-level simulation with GP-GPUs
Proceedings of the Conference on Design, Automation and Test in Europe
parSC: synchronous parallel systemc simulation on multi-core host architectures
CODES/ISSS '10 Proceedings of the eighth IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
SCGPSim: a fast SystemC simulator on GPUs
Proceedings of the 2010 Asia and South Pacific Design Automation Conference
SAGA: SystemC acceleration on GPU architectures
Proceedings of the 49th Annual Design Automation Conference
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
A hierarchical compiled code event-driven logic simulator
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
SystemC simulation on GP-GPUs: CUDA vs. OpenCL
Proceedings of the eighth IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
FAST-GP: an RTL functional verification framework based on fault simulation on GP-GPUs
DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
| Hi-index | 0.00 |
General purpose graphics processing units (GP-GPUs) have recently been explored as a new computing paradigm for accelerating compute-intensive EDA applications. Such massively parallel architectures have been applied in accelerating the simulation of digital designs during several phases of their development -- corresponding to different abstraction levels, specifically: (i) gate-level netlist descriptions, (ii) register-transfer level and (iii) transaction-level descriptions. This embedded tutorial presents a comprehensive analysis of the best results obtained by adopting GP-GPUs in all these EDA applications.