Communicating sequential processes
Communicating sequential processes
High-level synthesis: introduction to chip and system design
High-level synthesis: introduction to chip and system design
Synthesis and Optimization of Digital Circuits
Synthesis and Optimization of Digital Circuits
Efficient simulation of synthesis-oriented system level designs
Proceedings of the 15th international symposium on System Synthesis
Proceedings of the conference on Design, automation and test in Europe
An Esterel compiler for large control-dominated systems
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
On the use of GP-GPUs for accelerating compute-intensive EDA applications
Proceedings of the Conference on Design, Automation and Test in Europe
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This chapter describes algorithmic ways to transform a multi-threaded SystemC model into a non-threaded model for simulation efficiency. Such a transformation must be correctness preserving, and the transformed model must simulate the original model. We show simulation results to establish the efficiency enhancement by the systematic transformation.