COSMOS: a compiled simulator for MOS circuits
DAC '87 Proceedings of the 24th ACM/IEEE Design Automation Conference
High performance parallel logic simulations on a network of workstations
PADS '93 Proceedings of the seventh workshop on Parallel and distributed simulation
Parallel logic simulation on general purpose machines
DAC '88 Proceedings of the 25th ACM/IEEE Design Automation Conference
Exploiting parallelism in a switch-level simulation machine
DAC '86 Proceedings of the 23rd ACM/IEEE Design Automation Conference
Writing testbenches: functional verification of HDL models
Writing testbenches: functional verification of HDL models
Synthesis and Optimization of Digital Circuits
Synthesis and Optimization of Digital Circuits
Distributed VLSI Simulation on a Network of Workstations
ICCD '92 Proceedings of the 1991 IEEE International Conference on Computer Design on VLSI in Computer & Processors
Parallel Logic Simulation Using Time Warp on Shared-Memory Multiprocessors
Proceedings of the 8th International Symposium on Parallel Processing
The Yorktown Simulation Engine
DAC '82 Proceedings of the 19th Design Automation Conference
Communication-efficient hardware acceleration for fast functional simulation
Proceedings of the 41st annual Design Automation Conference
Comprehensive Functional Verification: The Complete Industry Cycle (Systems on Silicon)
Comprehensive Functional Verification: The Complete Industry Cycle (Systems on Silicon)
Towards acceleration of fault simulation using graphics processing units
Proceedings of the 45th annual Design Automation Conference
Distributed time, conservative parallel logic simulation on GPUs
Proceedings of the 47th Design Automation Conference
Multicore parallelization of min-cost flow for CAD applications
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems - Special section on the ACM IEEE international conference on formal methods and models for codesign (MEMOCODE) 2009
Parallel cross-layer optimization of high-level synthesis and physical design
Proceedings of the 16th Asia and South Pacific Design Automation Conference
Massively Parallel Logic Simulation with GPUs
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Gate-Level Simulation with GPU Computing
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Towards accelerating irregular EDA applications with GPUs
Integration, the VLSI Journal
Accelerating RTL simulation with GPUs
Proceedings of the International Conference on Computer-Aided Design
On the use of GP-GPUs for accelerating compute-intensive EDA applications
Proceedings of the Conference on Design, Automation and Test in Europe
FAST-GP: an RTL functional verification framework based on fault simulation on GP-GPUs
DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
On the automatic generation of GPU-oriented software applications from RTL IPs
Proceedings of the Ninth IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis
VarEMU: an emulation testbed for variability-aware software
Proceedings of the Ninth IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis
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In recent years, the verification of digital designs has become one of the most challenging, time consuming and critical tasks in the entire hardware development process. Within this area, the vast majority of the verification effort in industry relies on logic simulation tools. However, logic simulators deliver limited performance when faced with vastly complex modern systems, especially synthesized netlists. The consequences are poor design coverage, delayed product releases and bugs that escape into silicon. Thus, we developed a novel GPU-accelerated logic simulator, called GCS, optimized for large structural netlists. By leveraging the vast parallelism offered by GP-GPUs and a novel netlist balancing algorithm tuned for the target architecture, we can attain an order-of-magnitude performance improvement on average over commercial logic simulators, and simulate large industrial-size designs, such as the OpenSPARC processor core design.