Embedded tutorial: essential issues for IP reuse
ASP-DAC '00 Proceedings of the 2000 Asia and South Pacific Design Automation Conference
Towards acceleration of fault simulation using graphics processing units
Proceedings of the 45th annual Design Automation Conference
Event-driven gate-level simulation with GP-GPUs
Proceedings of the 46th Annual Design Automation Conference
Debunking the 100X GPU vs. CPU myth: an evaluation of throughput computing on CPU and GPU
Proceedings of the 37th annual international symposium on Computer architecture
Efficient fault simulation on many-core processors
Proceedings of the 47th Design Automation Conference
Parallel Cycle Based Logic Simulation Using Graphics Processing Units
ISPDC '10 Proceedings of the 2010 Ninth International Symposium on Parallel and Distributed Computing
GCS: high-performance gate-level simulation with GP-GPUs
Proceedings of the Conference on Design, Automation and Test in Europe
SCGPSim: a fast SystemC simulator on GPUs
Proceedings of the 2010 Asia and South Pacific Design Automation Conference
Designing APU Oriented Scientific Computing Applications in OpenCL
HPCC '11 Proceedings of the 2011 IEEE International Conference on High Performance Computing and Communications
On the Efficacy of a Fused CPU+GPU Processor (or APU) for Parallel Computing
SAAHPC '11 Proceedings of the 2011 Symposium on Application Accelerators in High-Performance Computing
SAGA: SystemC acceleration on GPU architectures
Proceedings of the 49th Annual Design Automation Conference
FAST-GP: an RTL functional verification framework based on fault simulation on GP-GPUs
DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
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Graphics processing units (GPUs) have been explored as a new computing paradigm for accelerating computation intensive applications. In particular, the combination between GPUs and CPU has proved to be an effective solution for accelerating the software execution, by mixing the few CPU cores optimized for serial processing with many smaller GPU cores designed for massively parallel computations. In addition, sustained by the need of low power consumption besides high performance, a recent trend is combining GPUs and CPU onto a single die (e.g., AMD Fusion, Intel Sandy Bridge, NVIDIA Tegra). The good trade-off between computing capability and power consumption makes the integrated GPUs a promising alternative for accelerating a wide range of software application for embedded systems. Nevertheless, algorithms must be redesigned to take advantage of these architectures and such a manual parallelization often results in being unsatisfactory. This paper presents a methodology to automatically generate software applications for GPUs, by reusing existing and pre-verified register-transfer level (RTL) intellectual-properties (IPs). The methodology aims at exploiting the intrinsic parallelism of RTL IPs (such as process concurrency and pipeline micro-architecture) for generating the parallel software implementation of the functionality. The experimental results show how the performance obtained by running the RTL functionality as software applications on GPUs outperform those provided by the RTL code mapped into a hardware accelerator.