LECSIM: a levelized event driven compiled logic simulation
DAC '90 Proceedings of the 27th ACM/IEEE Design Automation Conference
Use of embedded scheduling to compile VHDL for effective parallel simulation
EURO-DAC '95/EURO-VHDL '95 Proceedings of the conference on European design automation
A New Optimized Implemention of the SystemC Engine Using Acyclic Scheduling
Proceedings of the conference on Design, automation and test in Europe - Volume 1
Evaluation of SystemC Modelling of Reconfigurable Embedded Systems
Proceedings of the conference on Design, Automation and Test in Europe - Volume 3
Online SystemC emulation acceleration
Proceedings of the 47th Design Automation Conference
Dynamic acceleration management for SystemC emulation
ACM SIGBED Review - Special Issue on the 2nd International Workshop on Adaptive and Reconfigurable Embedded Systems (APRES'09)
SCGPSim: a fast SystemC simulator on GPUs
Proceedings of the 2010 Asia and South Pacific Design Automation Conference
Accelerating UNISIM-Based Cycle-Level Microarchitectural Simulations on Multicore Platforms
ACM Transactions on Design Automation of Electronic Systems (TODAES)
On the use of GP-GPUs for accelerating compute-intensive EDA applications
Proceedings of the Conference on Design, Automation and Test in Europe
Proceedings of the 50th Annual Design Automation Conference
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This paper presents a new approach that can be used to speed up SystemC simulations by automatically optimizing the model for simulation. The work addresses the inefficiency of the standard SystemC scheduler that may lead in some situations to unnecessary wake-up calls, as well as unnecessary code execution. The method presented analyzes the SystemC code to automatically extract signal dependencies based on a set of rules. This information is then used to split large processes into smaller ones. Process splitting is performed by a tool - SplitPro- which generates an optimized code that can be run on any standard SystemC engine. SplitPro was used to analyze the description of an Alpha super scalar processor and optimize some of its modules. A speed gain of up to 23% in simulation time was achieved over a number of split processes.