Parallel logic simulation of VLSI systems
ACM Computing Surveys (CSUR)
Parallel and Distribution Simulation Systems
Parallel and Distribution Simulation Systems
Pentium Processor System Architecture
Pentium Processor System Architecture
Distributed Simulation: A Case Study in Design and Verification of Distributed Programs
IEEE Transactions on Software Engineering
Relaxing Synchronization in a Parallel SystemC Kernel
ISPA '08 Proceedings of the 2008 IEEE International Symposium on Parallel and Distributed Processing with Applications
Parallelizing SystemC Kernel for Fast Hardware Simulation on SMP Machines
PADS '09 Proceedings of the 2009 ACM/IEEE/SCS 23rd Workshop on Principles of Advanced and Distributed Simulation
parSC: synchronous parallel systemc simulation on multi-core host architectures
CODES/ISSS '10 Proceedings of the eighth IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
The 48-core SCC Processor: the Programmer's View
Proceedings of the 2010 ACM/IEEE International Conference for High Performance Computing, Networking, Storage and Analysis
A conservative approach to systemc parallelization
ICCS'06 Proceedings of the 6th international conference on Computational Science - Volume Part IV
HLA-based simulation environment for distributed SystemC simulation
Proceedings of the 4th International ICST Conference on Simulation Tools and Techniques
Hi-index | 0.00 |
Since the number of cores integrated on a single die is expected to increase steadily, new memory and communication architectures as well as programming methods are needed and currently explored by manufacturers. In this context, Intel Labs developed the Single-chip Cloud Computer (SCC), a 48-core experimental processor, serving as a platform for many-core software research. Within this paper a framework targeting the investigation of SystemC kernel parallelization on the SCC is presented. The framework provides the basis for implementation of different synchronization schemes while combining distributed and shared memory programming models and exploiting multiple distinct address spaces. As a case study, a synchronous parallelization scheme is preliminarily evaluated by means of several simulation models of different accuracy. Results of the analysis give a first evidence of the applicability of the synchronous parallelization method on the homogeneous non-cache coherent manycore architecture of the SCC for detailed system simulation.