An axiomatic basis for computer programming
Communications of the ACM
Dos and don'ts of CTL state coverage estimation
Proceedings of the 40th annual Design Automation Conference
Transaction level modeling: an overview
Proceedings of the 1st IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
An Integrated Design and Verification Methodology for Reconfigurable Multimedia Systems
Proceedings of the conference on Design, Automation and Test in Europe - Volume 3
Combining System Level Modeling with Assertion Based Verification
ISQED '05 Proceedings of the 6th International Symposium on Quality of Electronic Design
Design and implementation of transducer for ARM-TMS communication
ASP-DAC '06 Proceedings of the 2006 Asia and South Pacific Design Automation Conference
On the evaluation of transactor-based verification for reusing TLM assertions and testbenches at RTL
Proceedings of the conference on Design, automation and test in Europe: Proceedings
Towards an efficient assertion based verification of SystemC designs
HLDVT '04 Proceedings of the High-Level Design Validation and Test Workshop, 2004. Ninth IEEE International
Properties Incompleteness Evaluation by Functional Verification
IEEE Transactions on Computers
Integrating RTL IPs into TLM designs through automatic transactor generation
Proceedings of the conference on Design, automation and test in Europe
A fast MPI-based parallel framework for cycle-accurate HDL multi-parametric simulations
International Journal of High Performance Systems Architecture
SystemC simulation on GP-GPUs: CUDA vs. OpenCL
Proceedings of the eighth IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
A systematic approach to configurable functional verification of HW IP blocks at transaction level
Computers and Electrical Engineering
Automatic refinement of requirements for verification throughout the SoC design flow
Proceedings of the Ninth IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis
Diagnosing root causes of system level performance violations
Proceedings of the International Conference on Computer-Aided Design
Automatic Generation of System Level Assertions from Transaction Level Models
Journal of Electronic Testing: Theory and Applications
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Transaction-level modeling (TLM) has been proposed as the leading strategy to address the ever-increasing complexity of digital systems. However, its introduction brings a new challenge for designers and verification engineers. Because no tools are available to automatically derive an RTL implementation from a transaction-level (TL) design, manual refinements are necessary. This article presents a hybrid, incremental assertion-based verification (ABV) methodology to check the correctness of the TL-to-RTL refinement. The methodology relies on reusing assertions and already-checked code and is guided by assertion coverage metrics.