On behavior fault modeling for digital designs
Journal of Electronic Testing: Theory and Applications
Symbolic Model Checking
Art of Software Testing
Logic Synthesis and Verification Algorithms
Logic Synthesis and Verification Algorithms
FoCs: Automatic Generation of Simulation Checkers from Formal Specifications
CAV '00 Proceedings of the 12th International Conference on Computer Aided Verification
RTL-Based Functional Test Generation for High Defects Coverage in Digital SOCs
ETW '00 Proceedings of the IEEE European Test Workshop
Verification of Transaction-Level SystemC models using RTL Testbenches
MEMOCODE '03 Proceedings of the First ACM and IEEE International Conference on Formal Methods and Models for Co-Design
Transaction level modeling: an overview
Proceedings of the 1st IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
A Proposal for Transaction-Level Verification with Component Wrapper Language
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe: Designers' Forum - Volume 2
Design for Verification of SystemC Transaction Level Models
Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Combining System Level Modeling with Assertion Based Verification
ISQED '05 Proceedings of the 6th International Symposium on Quality of Electronic Design
Coverage of Formal Properties Based on a High-Level Fault Model and Functional ATPG
ETS '05 Proceedings of the 10th IEEE European Symposium on Test
On PSL Properties Re-use in SoC Design Flow Based on Transaction Level Modeling
MTV '05 Proceedings of the Sixth International Workshop on Microprocessor Test and Verification
Incremental ABV for functional validation of TL-to-RTL design refinement
Proceedings of the conference on Design, automation and test in Europe
Hybrid, Incremental Assertion-Based Verification for TLM Design Flows
IEEE Design & Test
Graph based test case generation for TLM functional verification
Microprocessors & Microsystems
Modeling software requirement with timing diagram and Simulink Stateflow
Information and Software Technology
Hardware design and simulation for verification
SFM'06 Proceedings of the 6th international conference on Formal Methods for the Design of Computer, Communication, and Software Systems
Automatic RTL Test Generation from SystemC TLM Specifications
ACM Transactions on Embedded Computing Systems (TECS)
On the Reuse of TLM Mutation Analysis at RTL
Journal of Electronic Testing: Theory and Applications
FAST: An RTL Fault Simulation Framework based on RTL-to-TLM Abstraction
Journal of Electronic Testing: Theory and Applications
| Hi-index | 0.00 |
Transaction level modeling (TLM) is becoming an usual practice for simplifying system-level design and architecture exploration. It allows the designers to focus on the functionality of the design, while abstracting away implementation details that will be added at lower abstraction levels. However, moving from transaction level to RTL requires to redefine TLM testbenches and assertions. Such a wasteful and error prone conversion can be avoided by adopting transactor-based verification (TBV). Many recent works adopt this strategy to propose verification methodologies that allow (1) mixing TLM and RTL components, and (2) reusing TLM assertions and testbenches at RTL. Even if practical advantages of such an approach are evident, there are no papers in the literature that evaluate the effectiveness of the TBV compared to a more traditional RTL verification strategy. This paper is intended to fill in the gap. It theoretically compares the quality of the TBV towards the rewriting of assertions and testbenches at RTL with respect to both fault coverage and assertion coverage.