Introduction to HOL: a theorem proving environment for higher order logic
Introduction to HOL: a theorem proving environment for higher order logic
Evolving algebras 1993: Lipari guide
Specification and validation methods
YAML: a tool for hardware design visualization and capture
ISSS '00 Proceedings of the 13th international symposium on System synthesis
SystemC: methodologies and applications
SystemC: methodologies and applications
Object-oriented modeling and synthesis of SystemC specifications
Proceedings of the 2004 Asia and South Pacific Design Automation Conference
Application of UML for hardware design based on design process model
Proceedings of the 2004 Asia and South Pacific Design Automation Conference
Incorporating Ef.cient Assertion Checkers into Hardware Emulation
ICCD '05 Proceedings of the 2005 International Conference on Computer Design
Efficient assertion based verification using TLM
Proceedings of the conference on Design, automation and test in Europe: Proceedings
On the evaluation of transactor-based verification for reusing TLM assertions and testbenches at RTL
Proceedings of the conference on Design, automation and test in Europe: Proceedings
An assertion-based verification methodology for system-level design
Computers and Electrical Engineering
Incremental ABV for functional validation of TL-to-RTL design refinement
Proceedings of the conference on Design, automation and test in Europe
Partial order reduction for scalable testing of systemC TLM designs
Proceedings of the 45th annual Design Automation Conference
On the Transformation of SystemC to AsmL Using Abstract Interpretation
Electronic Notes in Theoretical Computer Science (ENTCS)
Design and verification of systemc transaction-level models
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A multi-encoding approach for LTL symbolic satisfiability checking
FM'11 Proceedings of the 17th international conference on Formal methods
An approach for the verification of systemc designs using asml
ATVA'05 Proceedings of the Third international conference on Automated Technology for Verification and Analysis
TwinsNet: a cooperative MIMO mobile sensor network
UIC'06 Proceedings of the Third international conference on Ubiquitous Intelligence and Computing
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Transaction level modeling allows exploring several SoC design architectures leading to better performance and easier verification of the final product. In this paper, we present an approach to design and verify SystemC models at the transaction level. We integrate the verification as part of the design-flow. In the proposed approach, we first model both the design and the properties (written in PSL) in UML. Then, we translate them into an intermediate format modeled with Abstract State Machines (ASM). The ASM model is used to generate an FSM of the design including the properties. Checking the correctness of the properties is performed on-the-fly while generating the state machine. Finally, we translate the verified design to SystemC and map the properties to a set of assertions (as monitors in C#) that can be re-used to validate the design at lower levels through simulation. We illustrate our approach on two case studies including the PCI bus standard and a generic Master/Slave architecture from the SystemC library.