Evolving algebras 1993: Lipari guide
Specification and validation methods
Tool-supported program abstraction for finite-state verification
ICSE '01 Proceedings of the 23rd International Conference on Software Engineering
Systematic design of program transformation frameworks by abstract interpretation
POPL '02 Proceedings of the 29th ACM SIGPLAN-SIGACT symposium on Principles of programming languages
Generating finite state machines from abstract state machines
ISSTA '02 Proceedings of the 2002 ACM SIGSOFT international symposium on Software testing and analysis
Monitor-Based Formal Specification of PCI
FMCAD '00 Proceedings of the Third International Conference on Formal Methods in Computer-Aided Design
Verification Tools for Finite-State Concurrent Systems
A Decade of Concurrency, Reflections and Perspectives, REX School/Symposium
Abstract State Machines: A Method for High-Level System Design and Analysis
Abstract State Machines: A Method for High-Level System Design and Analysis
Design for Verification of SystemC Transaction Level Models
Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
On the Design and Verification Methodology of the Look-Aside Interface
Proceedings of the conference on Design, Automation and Test in Europe - Volume 3
Spin model checker, the: primer and reference manual
Spin model checker, the: primer and reference manual
Model checking SystemC designs using timed automata
CODES+ISSS '08 Proceedings of the 6th IEEE/ACM/IFIP international conference on Hardware/Software codesign and system synthesis
Combining Model Checking and Testing in a Continuous HW/SW Co-verification Process
TAP '09 Proceedings of the 3rd International Conference on Tests and Proofs
Formal Analysis of SystemC Designs in Process Algebra
Fundamenta Informaticae
A HW/SW co-verification framework for SystemC
ACM Transactions on Embedded Computing Systems (TECS) - Special section on ESTIMedia'12, LCTES'11, rigorous embedded systems design, and multiprocessor system-on-chip for cyber-physical systems
| Hi-index | 0.00 |
The spectacular advancement in microelectronics resulted in the creation of new system level design languages, such as SystemC, which put fourth new design and verification challenges. In this paper, we present an approach verifying SystemC designs using model checking and assertion based verification. Such verification is enabled through two transformations from SystemC to AsmL (the Abstract State Machines Language) and vice-versa. The soundness of these transformations, proved using abstract interpretation, guarantees the correctness of the model checking results and the validity of the generated assertion monitors (to be checked by simulation). We illustrate our approach on the SystemC/AsmL modeling and verification of the widely used Accelerated Graphics Port (AGP) standard. The verified AGP model can be either refined to implement an AGP core or used to validate existent compatible device.