On the evaluation of transactor-based verification for reusing TLM assertions and testbenches at RTL
Proceedings of the conference on Design, automation and test in Europe: Proceedings
Incremental ABV for functional validation of TL-to-RTL design refinement
Proceedings of the conference on Design, automation and test in Europe
Reuse and optimization of testbenches and properties in a TLM-to-RTL design flow
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Hardware design and simulation for verification
SFM'06 Proceedings of the 6th international conference on Formal Methods for the Design of Computer, Communication, and Software Systems
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The use of model checking to validate descriptions of digital systems lacks a coverage metrics. If the set of formal properties defined to prove the correctness of the design is incomplete, the verification can lead to a false sense of security. This paper refines, extends, and compares with other symbolic approaches, a methodology to estimate the incompleteness of formal properties, which exploits a high-level fault model and functional ATPG.