On the evaluation of transactor-based verification for reusing TLM assertions and testbenches at RTL
Proceedings of the conference on Design, automation and test in Europe: Proceedings
TLM/network design space exploration for networked embedded systems
CODES+ISSS '06 Proceedings of the 4th international conference on Hardware/software codesign and system synthesis
Incremental ABV for functional validation of TL-to-RTL design refinement
Proceedings of the conference on Design, automation and test in Europe
Reuse and optimization of testbenches and properties in a TLM-to-RTL design flow
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Hardware design and simulation for verification
SFM'06 Proceedings of the 6th international conference on Formal Methods for the Design of Computer, Communication, and Software Systems
Automatic refinement of requirements for verification throughout the SoC design flow
Proceedings of the Ninth IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis
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The ability to enhance single-thread performance, such as by increasing clock frequency, is reaching a point of diminishing returns: power is becoming a dominating factor and limiting scalability. Adding additional cores is a scalable way to increase ...