Processor Allocation in the Mesh Multiprocessors Using the Leapfrog Method
IEEE Transactions on Parallel and Distributed Systems
FIT - A Parallel Hierarchical Fault Simulation Environment
PARELEC '04 Proceedings of the international conference on Parallel Computing in Electrical Engineering
Key research problems in NoC design: a holistic perspective
CODES+ISSS '05 Proceedings of the 3rd IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
Hybrid, Incremental Assertion-Based Verification for TLM Design Flows
IEEE Design & Test
A Novel Non-exclusive Dual-Mode Architecture for MPSoCs-Oriented Network on Chip Designs
SAMOS '08 Proceedings of the 8th international workshop on Embedded Computer Systems: Architectures, Modeling, and Simulation
Impact of Half-Duplex and Full-Duplex DMA Implementations on NoC Performance
NOCS '10 Proceedings of the 2010 Fourth ACM/IEEE International Symposium on Networks-on-Chip
Concurrent hybrid switching for massively parallel systems-on-chip: the CYBER architecture
Proceedings of the 9th conference on Computing Frontiers
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The growing complexity of digital architectures strongly impacts on their verification phase, which becomes critical. In fact, without giving up cycle-accuracy, it seems there are not at the state-of-the-art fast frameworks allowing multi-parametric simulations at a fine granularity level for accurate verification and design space exploration purposes. In this paper, we propose a parallel, fast and cycle-accurate SystemC simulation framework: SysCgrid. SysCgrid is designed to provide automatic generation and parallel execution of multi-parametric simulations with minimum effort by hardware architects. This framework is conceived to run on a cluster/grid computing infrastructure, exploiting the message passing interface (MPI) to automatically distribute the multi-parametric simulation set over more than one node. The achieved results on a network-on-chip (NoC) architecture verification demonstrate the good SysCgrid scalability, both in case of shared and non-shared memory computing infrastructures, achieving impressive speed up with respect to traditional single-run simulations approaches.