Programming in Prolog
Contracts: specifying behavioral compositions in object-oriented systems
OOPSLA/ECOOP '90 Proceedings of the European conference on object-oriented programming on Object-oriented programming systems, languages, and applications
Writing testbenches: functional verification of HDL models
Writing testbenches: functional verification of HDL models
Introduction to Formal Hardware Verification: Methods and Tools for Designing Correct Circuits and Systems
Embedded System Design: A Unified Hardware/Software Introduction
Embedded System Design: A Unified Hardware/Software Introduction
Logic Minimization Algorithms for VLSI Synthesis
Logic Minimization Algorithms for VLSI Synthesis
Use Case Maps for the Capture and Validation of Distributed Systems Requirements
RE '99 Proceedings of the 4th IEEE International Symposium on Requirements Engineering
VIATRA " Visual Automated Transformations for Formal Verification and Validation of UML Models
Proceedings of the 17th IEEE international conference on Automated software engineering
A UML Validation Toolset Based on Abstract State Machines
Proceedings of the 16th IEEE international conference on Automated software engineering
System Verilog for Design: A Guide to Using System Verilog for Hardware Design and Modeling
System Verilog for Design: A Guide to Using System Verilog for Hardware Design and Modeling
GOOAL: a Graphic Object Oriented Analysis Laboratory
OOPSLA '02 Companion of the 17th annual ACM SIGPLAN conference on Object-oriented programming, systems, languages, and applications
Specifying and analyzing early requirements in Tropos
Requirements Engineering
Consistency Validation of High-Level Requirements
IWSOC '04 Proceedings of the System-on-Chip for Real-Time Applications, 4th IEEE International Workshop
Proceedings of the conference on Design, Automation and Test in Europe - Volume 2
Transaction Level Modeling: Flows and Use Models
CODES+ISSS '04 Proceedings of the international conference on Hardware/Software Codesign and System Synthesis: 2004
Introductory VHDL: From Simulation To Synthesis
Introductory VHDL: From Simulation To Synthesis
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Current electronic systems' complexity severely limits their validation. Even if development frameworks keep improving and are heavily supported by the industry, methods for hardware/software electronic systems co-design are reaching a major crisis. Although the community is heading towards higher abstraction levels, requirements remain out of the validation scope. We therefore present a requirements engineering methodology that intersects formal, linguistic, and scenario views. Modeling consists in abstracting functionalities' behaviours in terms of actions, expressed in a semi-formal structured language, later automatically translated in a pure formal notation. Such a mix makes the language accessible to designers and permits automation. Validation is then performed using consistency rules. Finally, an elicitation of missing functionalities is achieved using Boolean algebra.