Cache design trade-offs for power and performance optimization: a case study
ISLPED '95 Proceedings of the 1995 international symposium on Low power design
Analysis of power consumption in memory hierarchies
ISLPED '97 Proceedings of the 1997 international symposium on Low power electronics and design
MediaBench: a tool for evaluating and synthesizing multimedia and communicatons systems
MICRO 30 Proceedings of the 30th annual ACM/IEEE international symposium on Microarchitecture
Memory system characterization of commercial workloads
Proceedings of the 25th annual international symposium on Computer architecture
Power and performance tradeoffs using various caching strategies
ISLPED '98 Proceedings of the 1998 international symposium on Low power electronics and design
In-memory data management for consumer transactions the timesten approach
SIGMOD '99 Proceedings of the 1999 ACM SIGMOD international conference on Management of data
Power efficient mediaprocessors: design space exploration
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Wattch: a framework for architectural-level power analysis and optimizations
Proceedings of the 27th annual international symposium on Computer architecture
A design framework to efficiently explore energy-delay tradeoffs
Proceedings of the ninth international symposium on Hardware/software codesign
ISCA '01 Proceedings of the 28th annual international symposium on Computer architecture
L1 data cache decomposition for energy efficiency
ISLPED '01 Proceedings of the 2001 international symposium on Low power electronics and design
Critical power slope: understanding the runtime effects of frequency scaling
ICS '02 Proceedings of the 16th international conference on Supercomputing
Saving energy with architectural and frequency adaptations for multimedia applications
Proceedings of the 34th annual ACM/IEEE international symposium on Microarchitecture
Proceedings of the 34th annual ACM/IEEE international symposium on Microarchitecture
Analyzing energy behavior of spatial access methods for memory-resident data
Proceedings of the 27th International Conference on Very Large Data Bases
Adaptive Mode Control: A Static-Power-Efficient Cache Design
Proceedings of the 2001 International Conference on Parallel Architectures and Compilation Techniques
A system-level methodology for fast multi-objective design space exploration
Proceedings of the 13th ACM Great Lakes symposium on VLSI
Multi-objective design space exploration using genetic algorithms
Proceedings of the tenth international symposium on Hardware/software codesign
Proceedings of the 2004 ACM symposium on Applied computing
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Microprocessor design is a considerably complex task. First, microprocessors include many resources that may be configured in different ways. This leads to a time consuming multi-objective optimization problem. Second, currently the designs must take into account not only performance but also power consumption thus making the optimization goal more complex. Third, different types of applications have different demands but producing several different microprocessors would not be cost effective. This paper proposes an efficient algorithm to explore the design space: design space navigation. With this algorithm it is possible to obtain optimal configurations by starting from a baseline and “navigating” on the design space. Different configurations tailored for different applications, but derived from the same baseline, are called neighboring configurations. Experimental results show that navigation finds designs that achieve better power-performance efficiency for a fraction of the time required by other design space exploration algorithms. Also, the algorithm is used to obtain four neighboring configurations for four types of applications: multimedia, integer and floating-point scientific, and database workloads. The results showed that the navigation configuration achieves a power-performance improvement of 30% to 118% depending on the workload. Using different workloads for navigation and execution may result in a loss of efficiency of as much as 94%.