Designing the M·CORETM M3 CPU Architecture
ICCD '99 Proceedings of the 1999 IEEE International Conference on Computer Design
Proceedings of the 2004 ACM symposium on Applied computing
Multi-Objective Design Space Exploration Methodologies for Platform based SOCs
ECBS '06 Proceedings of the 13th Annual IEEE International Symposium and Workshop on Engineering of Computer Based Systems
Application-specific customization of parameterized FPGA soft-core processors
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
Multi-objective design space exploration of embedded systems
Journal of Embedded Computing - Low-power Embedded Systems
Multiobjective evolutionary algorithms: a comparative case studyand the strength Pareto approach
IEEE Transactions on Evolutionary Computation
IEEE Transactions on Evolutionary Computation
Platune: a tuning framework for system-on-a-chip platforms
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
A multiobjective genetic approach for system-level exploration in parameterized systems-on-a-chip
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Near-Optimal Microprocessor and Accelerators Codesign with Latency and Throughput Constraints
ACM Transactions on Architecture and Code Optimization (TACO)
Exploration with upgradeable models using statistical methods for physical model emulation
Proceedings of the 50th Annual Design Automation Conference
Fast Design Exploration for Performance, Power and Accuracy Tradeoffs in FPGA-Based Accelerators
ACM Transactions on Reconfigurable Technology and Systems (TRETS)
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Field-programmable gate arrays (FPGAs) commonly implement system architectures composed from soft-core configurable components, such as a cache with configurable size or associativity, a processor with configurable datapath units, or a configurable network-on-chip connecting dozens of processors. Configurable components increasingly exist even on pre-fabricated platforms. Tuning configurable components to the particular application running on the architecture and to particular design constraints represents a challenging task often left to a designer. Knowledge of the Pareto-optimal points of a system for particular applications can be of benefit to designers seeking to make appropriate design tradeoffs for given constraints. Previous methods for generating Pareto points required extensive knowledge of an architecture's parameter interdependencies, used a simplistic approach that failed to find many parameters, or used randomized search algorithms that may have long runtimes. We introduce an algorithm for finding Pareto points, based on statistically rigorous methods derived from the Design of Experiments paradigm and extended for the purpose of finding Pareto points. The resulting DoE-based Pareto point Generator, or DPG, algorithm finds thorough Pareto points while running 3 times faster than randomized search algorithms, without requiring designer knowledge of parameter interdependencies--in fact, the approach determines those interdependencies automatically, representing an added bonus. We demonstrate DPG on Platune's configurable processor-bus-cache system-on-chip, Noxim's configurable network-on-chip, and the configurable Microblaze FPGA processor.