Proceedings of the 38th annual Design Automation Conference
System-level exploration for pareto-optimal configurations in parameterized systems-on-a-chip
Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design
System synthesis of synchronous multimedia applications
ACM Transactions on Embedded Computing Systems (TECS)
Temperature-aware microarchitecture
Proceedings of the 30th annual international symposium on Computer architecture
Energy-Efficient Mapping and Scheduling for DVS Enabled Distributed Embedded Systems
Proceedings of the conference on Design, automation and test in Europe
An Algorithm-Based Error Detection Scheme for the Multigrid Method
IEEE Transactions on Computers
Efficient Thermal Placement of Standard Cells in 3D ICs using a Force Directed Approach
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Architecting voltage islands in core-based system-on-a-chip designs
Proceedings of the 2004 international symposium on Low power electronics and design
Architecting voltage islands in core-based system-on-a-chip designs
Proceedings of the 2004 international symposium on Low power electronics and design
Temperature-aware resource allocation and binding in high-level synthesis
Proceedings of the 42nd annual Design Automation Conference
A thermal-driven floorplanning algorithm for 3D ICs
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
Efficient full-chip thermal modeling and analysis
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
TAPHS: thermal-aware unified physical-level and high-level synthesis
ASP-DAC '06 Proceedings of the 2006 Asia and South Pacific Design Automation Conference
Interconnect and Thermal-aware Floorplanning for 3D Microprocessors
ISQED '06 Proceedings of the 7th International Symposium on Quality Electronic Design
Exploring "temperature-aware" design in low-power MPSoCs
Proceedings of the conference on Design, automation and test in Europe: Proceedings
The M5 Simulator: Modeling Networked Systems
IEEE Micro
Three-dimensional integrated circuits
IBM Journal of Research and Development - Advanced silicon technology
Die Stacking (3D) Microarchitecture
Proceedings of the 39th Annual IEEE/ACM International Symposium on Microarchitecture
Journal of VLSI Signal Processing Systems
Accurate temperature-dependent integrated circuit leakage power estimation is easy
Proceedings of the conference on Design, automation and test in Europe
ISAC: Integrated Space-and-Time-Adaptive Chip-Package Thermal Analysis
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Proceedings of the 2009 Asia and South Pacific Design Automation Conference
Outstanding research problems in NoC design: system, microarchitecture, and circuit perspectives
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Dynamic thermal management in 3D multicore architectures
Proceedings of the Conference on Design, Automation and Test in Europe
Low-energy automated scheduling of computing resources
Proceedings of the 1st ACM/IEEE workshop on Autonomic computing in economics
Recent thermal management techniques for microprocessors
ACM Computing Surveys (CSUR)
Reliability-aware platform optimization for 3D chip multi-processors
The Journal of Supercomputing
Design-time performance evaluation of thermal management policies for SRAM and RRAM based 3D MPSoCs
Proceedings of the great lakes symposium on VLSI
Thermal-aware real-time task scheduling for three-dimensional multicore chip
Proceedings of the 27th Annual ACM Symposium on Applied Computing
Cooperative boosting: needy versus greedy power management
Proceedings of the 40th Annual International Symposium on Computer Architecture
Thermal-constrained task allocation for interconnect energy reduction in 3-D homogeneous MPSoCs
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Throughput maximization for periodic real-time systems under the maximal temperature constraint
ACM Transactions on Embedded Computing Systems (TECS) - Special Section ESFH'12, ESTIMedia'11 and Regular Papers
| Hi-index | 0.00 |
3D stacked wafer integration has the potential to improve multiprocessor system-on-chip (MPSoC) integration density, performance, and power efficiency. However, the power density of 3D MPSoCs increases with the number of active layers, resulting in high chip temperatures. This can reduce system reliability, reduce performance, and increase cooling cost. Thermal optimization for 3D MPSoCs imposes numerous challenges. It is difficult to manage assignment and scheduling of heterogeneous workloads to maintain thermal safety. In addition, the thermal characteristics of 3D MPSoCs differ from those of 2D MPSoCs because each stacked layer has a different thermal resistance to the ambient and vertically-adjacent processors have strong temperature correlation. We propose a 3D MPSoC thermal optimization algorithm that conducts task assignment, scheduling, and voltage scaling. A power balancing algorithm is initially used to distribute tasks among cores and active layers. Detailed thermal analysis is used to guide a hotspot mitigation algorithm that incrementally reduces the peak MPSoC temperature by appropriately adjusting task execution times and voltage levels. The proposed algorithm considers leakage power consumption and adapts to inter-layer thermal heterogeneity. Performance evaluation on a set of multiprogrammed and multithreaded benchmarks indicates that the proposed techniques can optimize 3DMPSoC power consumption, power profile, and chip peak temperature.