COMPCON '92 Proceedings of the thirty-seventh international conference on COMPCON
On the characterization of VBR MPEG streams
SIGMETRICS '97 Proceedings of the 1997 ACM SIGMETRICS international conference on Measurement and modeling of computer systems
Application-driven synthesis of core-based systems
ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design
Predicting MPEG execution times
SIGMETRICS '98/PERFORMANCE '98 Proceedings of the 1998 ACM SIGMETRICS joint international conference on Measurement and modeling of computer systems
Scheduling Algorithms for Multiprogramming in a Hard-Real-Time Environment
Journal of the ACM (JACM)
Energy minimization with guaranteed quality of service
ISLPED '00 Proceedings of the 2000 international symposium on Low power electronics and design
Dynamic voltage scheduling technique for low-power multimedia applications using buffers
ISLPED '01 Proceedings of the 2001 international symposium on Low power electronics and design
A framework for reconfigurable computing: task scheduling and context management
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - System Level Design
Storage Allocation Policies for Time-Dependent Multimedia Data
IEEE Transactions on Knowledge and Data Engineering
A Distributed Real-Time MPEG Video Audio Player
NOSSDAV '95 Proceedings of the 5th International Workshop on Network and Operating System Support for Digital Audio and Video
The Quality of Service Model and High Assurance
HASE '97 Proceedings of the 2nd High-Assurance Systems Engineering Workshop
A resource allocation model for QoS management
RTSS '97 Proceedings of the 18th IEEE Real-Time Systems Symposium
Quality of Service and System Design
WVLSI '99 Proceedings of the IEEE Computer Society Workshop on VLSI'99
Statistical characteristics and multiplexing of MPEG streams
INFOCOM '95 Proceedings of the Fourteenth Annual Joint Conference of the IEEE Computer and Communication Societies (Vol. 2)-Volume - Volume 2
A Buffer Merging Technique for Reducing Memory Requirements of Synchronous Dataflow Specifications
Proceedings of the 12th international symposium on System synthesis
Scheduling for quality of service guarantees via service curves
ICCCN '95 Proceedings of the 4th International Conference on Computer Communications and Networks
Voltage Scaling for Energy Minimization with QoS Constraints
ICCD '01 Proceedings of the International Conference on Computer Design: VLSI in Computers & Processors
Power optimization of variable-voltage core-based systems
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
IEEE Journal on Selected Areas in Communications
Quality of service guarantees in virtual circuit switched networks
IEEE Journal on Selected Areas in Communications
Three-dimensional multiprocessor system-on-chip thermal optimization
CODES+ISSS '07 Proceedings of the 5th IEEE/ACM international conference on Hardware/software codesign and system synthesis
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Modern system design is being increasingly driven by applications such as multimedia and wireless sensing and communications, which have intrinsic quality of service (QoS) requirements, such as throughput, error-rate, and resolution. One of the most crucial QoS guarantees that the system has to provide is the timing constraint among the interacting media (synchronization) and within each media (latency). We have developed the first framework for system design with timing QoS guarantees. In particular, we address how to design system-on-chip with minimum silicon area to meet both latency and synchronization constraints. The proposed design methodology consists of two phases: hardware configuration selection and on-chip memory/storage minimization. In the first phase, we use silicon area and system performance as criteria to identify all the competitive hardware configurations (i.e., Pareto points) that facilitate the needs of synchronous applications. In the second phase, we determine the minimum on-chip memory requirement to meet the timing constraints for each Pareto point. An overall system evaluation is conducted to select the best system configuration. We have developed optimal algorithms that schedule a priori specified applications to meet their synchronization requirements with the minimum size of memory. We have also implemented on-line heuristics for real-time applications. The effectiveness of our algorithms has been demonstrated on a set of simulated MPEG streams from popular movies.