A Case for Direct-Mapped Caches
Computer
Cache write policies and performance
ISCA '93 Proceedings of the 20th annual international symposium on computer architecture
Shade: a fast instruction-set simulator for execution profiling
SIGMETRICS '94 Proceedings of the 1994 ACM SIGMETRICS conference on Measurement and modeling of computer systems
A path-based technique for estimating hardware runtime in HW/SW-cosynthesis
ISSS '95 Proceedings of the 8th international symposium on System synthesis
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
A case study in computer-aided co-design of embedded controllers
Design Automation for Embedded Systems
Address calculation for retargetable compilation and exploration of instruction-set architectures
DAC '96 Proceedings of the 33rd annual Design Automation Conference
Software—Practice & Experience
Computer Architecture: Pipelined and Parallel Processor Design
Computer Architecture: Pipelined and Parallel Processor Design
Computers and Intractability: A Guide to the Theory of NP-Completeness
Computers and Intractability: A Guide to the Theory of NP-Completeness
Hardware-Software Cosynthesis for Digital Systems
IEEE Design & Test
Issues in developing real-time multimedia applications for a multiprocessor system
WPDRTS '96 Proceedings of the 4th International Workshop on Parallel and Distributed Real-Time Systems
MediaBench: a tool for evaluating and synthesizing multimedia and communicatons systems
MICRO 30 Proceedings of the 30th annual ACM/IEEE international symposium on Microarchitecture
Power optimization of variable voltage core-based systems
DAC '98 Proceedings of the 35th annual Design Automation Conference
Memory exploration for low power, embedded systems
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Automatic and efficient evaluation of memory hierarchies for embedded systems
Proceedings of the 32nd annual ACM/IEEE international symposium on Microarchitecture
Memory bank customization and assignment in behavioral synthesis
ICCAD '99 Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design
Data memory design and exploration for low-power embedded systems
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Memory Design and Exploration for Low Power, Embedded Systems
Journal of VLSI Signal Processing Systems - Special issue on signal processing systems design and implementation
System synthesis of synchronous multimedia applications
ACM Transactions on Embedded Computing Systems (TECS)
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A Scalable Application-Specific Processor Synthesis Methodology
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Proceedings of the 4th ACM international conference on Embedded software
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We developed a new hierarchical modular approach for synthesis of area-minimal core-based data-intensive systems. The optimization approach employs a novel global least-constraining most-constrained heuristic to minimize the instruction cache misses for a given application, instruction cache size and organization. Based on this performance optimization technique, we constructed a strategy to search for a minimal-area processor core, and an instruction and data cache which satisfy the performance characteristics of a set of target applications. The synthesis platform integrates the existing modeling, profiling, and simulation tools with the developed system-level synthesis tools. The effectiveness of the approach is demonstrated on a variety of modern real-life multimedia and communication applications.