Thermal-constrained task allocation for interconnect energy reduction in 3-D homogeneous MPSoCs

Authors:
Yuanqing Cheng;Lei Zhang;Yinhe Han;Xiaowei Li
Affiliations:
Key Laboratory of Computer System and Architecture, Institute of Computing Technology, Chinese Academy of Sciences, Beijing, China;Key Laboratory of Computer System and Architecture, Institute of Computing Technology, Chinese Academy of Sciences, Beijing, China;Key Laboratory of Computer System and Architecture, Institute of Computing Technology, Chinese Academy of Sciences, Beijing, China;Key Laboratory of Computer System and Architecture, Institute of Computing Technology, Chinese Academy of Sciences, Beijing, China
Venue:
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Year:
2013

Citing 40
Cited 0

TGFF: task graphs for free

Proceedings of the 6th international workshop on Hardware/software codesign
Route packets, not wires: on-chip inteconnection networks

Proceedings of the 38th annual Design Automation Conference
A Compile-Time Scheduling Heuristic for Interconnection-Constrained Heterogeneous Processor Architectures

IEEE Transactions on Parallel and Distributed Systems
Thermal-Aware Task Allocation and Scheduling for Embedded Systems

Proceedings of the conference on Design, Automation and Test in Europe - Volume 2
Thermal via placement in 3D ICs

Proceedings of the 2005 international symposium on Physical design
Multi-Objective Mapping for Mesh-Based NoC Architectures

CODES+ISSS '04 Proceedings of the international conference on Hardware/Software Codesign and System Synthesis: 2004
Energy-aware mapping for tile-based NoC architectures under performance constraints

ASP-DAC '03 Proceedings of the 2003 Asia and South Pacific Design Automation Conference
Time and energy efficient mapping of embedded applications onto NoCs

Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Thermal Trends in Emerging Technologies

ISQED '06 Proceedings of the 7th International Symposium on Quality Electronic Design
3D floorplanning with thermal vias

Proceedings of the conference on Design, automation and test in Europe: Proceedings
Design and Management of 3D Chip Multiprocessors Using Network-in-Memory

Proceedings of the 33rd annual international symposium on Computer Architecture
Overview of the MPSoC design challenge

Proceedings of the 43rd annual Design Automation Conference
A novel dimensionally-decomposed router for on-chip communication in 3D architectures

Proceedings of the 34th annual international symposium on Computer architecture
Temperature aware task scheduling in MPSoCs

Proceedings of the conference on Design, automation and test in Europe
Interconnects in the third dimension: design challenges for 3D ICs

Proceedings of the 44th annual Design Automation Conference
Thermal-aware task scheduling at the system software level

ISLPED '07 Proceedings of the 2007 international symposium on Low power electronics and design
Three-dimensional multiprocessor system-on-chip thermal optimization

CODES+ISSS '07 Proceedings of the 5th IEEE/ACM international conference on Hardware/software codesign and system synthesis
Thermal Herding: Microarchitecture Techniques for Controlling Hotspots in High-Performance 3D-Integrated Processors

HPCA '07 Proceedings of the 2007 IEEE 13th International Symposium on High Performance Computer Architecture
A 5-GHz Mesh Interconnect for a Teraflops Processor

IEEE Micro
Power and reliability management of SoCs

IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Application mapping for chip multiprocessors

Proceedings of the 45th annual Design Automation Conference
Temperature-aware scheduling and assignment for hard real-time applications on MPSoCs

Proceedings of the conference on Design, automation and test in Europe
Defect tolerance in homogeneous manycore processors using core-level redundancy with unified topology

Proceedings of the conference on Design, automation and test in Europe
A Modified Simulated Annealing Algorithm for the Quadratic Assignment Problem

Informatica
Networks-on-Chip in a Three-Dimensional Environment: A Performance Evaluation

IEEE Transactions on Computers
Temperature aware task sequencing and voltage scaling

Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design
Networks-on-chip in emerging interconnect paradigms: Advantages and challenges

NOCS '09 Proceedings of the 2009 3rd ACM/IEEE International Symposium on Networks-on-Chip
Energy efficient application mapping to NoC processing elements operating at multiple voltage levels

NOCS '09 Proceedings of the 2009 3rd ACM/IEEE International Symposium on Networks-on-Chip
Outstanding research problems in NoC design: system, microarchitecture, and circuit perspectives

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Thermal-Aware Task Scheduling for 3D Multicore Processors

IEEE Transactions on Parallel and Distributed Systems
Thermal Driven Test Access Routing in Hyper-interconnected Three-Dimensional System-on-Chip

DFT '09 Proceedings of the 2009 24th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems
Paper: Robust taboo search for the quadratic assignment problem

Parallel Computing
Cost-effective slack allocation for lifetime improvement in NoC-based MPSoCs

Proceedings of the Conference on Design, Automation and Test in Europe
Dynamic thermal management in 3D multicore architectures

Proceedings of the Conference on Design, Automation and Test in Europe
An Efficient Power-Aware Optimization for Task Scheduling on NoC-based Many-core System

CIT '10 Proceedings of the 2010 10th IEEE International Conference on Computer and Information Technology
Vertical interconnects squeezing in symmetric 3D mesh network-on-chip

Proceedings of the 16th Asia and South Pacific Design Automation Conference
Hotspot: acompact thermal modeling methodology for early-stage VLSI design

IEEE Transactions on Very Large Scale Integration (VLSI) Systems
An abacus turn model for time/space-efficient reconfigurable routing

Proceedings of the 38th annual international symposium on Computer architecture
Energy- and performance-aware mapping for regular NoC architectures

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Three-Dimensional Chip-Multiprocessor Run-Time Thermal Management

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Quantified Score

Hi-index	0.00

Visualization

Abstract

3-D technology that stacks silicon dies with through silicon vias (TSVs) is a promising solution to overcome the interconnect scaling problem in giga-scale integrated circuits (ICs). Thermal dissipation is a major challenge for 3-D integration and prior thermal-balanced task scheduling methods for 3-D multiprocessor system-on-chips (MPSoCs) typically balance power gradient across vertical stacks based on the assumption of strong thermal correlation among processing cores within a stack. On the other hand, 3-D MPSoCs typically employ network-on-chip (NoC) as the communication infrastructure which consumes a large portion of the energy budget. As TSVs consume much less energy than horizontal links in 3-D MPSoCs when transmitting the same amount data due to the reduced interconnect distance between vertical adjacent cores, it motivates to allocate heavily communicating tasks within the same vertical stack as much as possible, and thus traffic is restricted in the third dimension to reduce interconnect energy. However, aggregating active tasks within the same stack probably exacerbates the power density and result in hot spots. In this paper, we explore the tradeoff between thermal and interconnect energy when allocating tasks in 3-D Homogeneous MPSoCs, and propose an efficient heuristic. Experimental results show that the proposed technique can reduce interconnect energy by more than 25% on average with almost the same peak temperature when compared with prior thermal-balanced solutions.