Energy efficient application mapping to NoC processing elements operating at multiple voltage levels

Authors:
Pavel Ghosh;Arunabha Sen;Alexander Hall
Affiliations:
Department of Computer Science and Engineering, Arizona State University, Tempe, USA;Department of Computer Science and Engineering, Arizona State University, Tempe, USA;Department of EECS, UC Berkeley, CA, USA
Venue:
NOCS '09 Proceedings of the 2009 3rd ACM/IEEE International Symposium on Networks-on-Chip
Year:
2009

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Abstract

An efficient technique for mapping application tasks to heterogeneous processing elements (PEs) on a Network-on-Chip (NoC) platform, operating at multiple voltage levels, is presented in this paper. The goal of the mapping is to minimize energy consumption subject to the performance constraints. Such a mapping involves solving several subproblems. Most of the research effort in this area often address these subproblems in a sequential fashion or a subset of them. We take a unified approach to the problem without compromising the solution time and provide techniques for optimal and heuristic solutions. We prove that the voltage assignment component of the problem itself is NP-hard and is inapproximable within any constant factor. Our optimal solution utilizes a Mixed Integer Linear Program (MILP) formulation of the problem. The heuristic utilizes MILP relaxation and randomized rounding. Experimental results based on E3S benchmark applications and a few real applications show that our heuristic produces near-optimal solution in a fraction of time needed to find the optimal.