A static power model for architects
Proceedings of the 33rd annual ACM/IEEE international symposium on Microarchitecture
Route packets, not wires: on-chip inteconnection networks
Proceedings of the 38th annual Design Automation Conference
Analysis of power consumption on switch fabrics in network routers
Proceedings of the 39th annual Design Automation Conference
Managing power and performance for System-on-Chip designs using Voltage Islands
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
Practical Design of Globally-Asynchronous Locally-Synchronous Systems
ASYNC '00 Proceedings of the 6th International Symposium on Advanced Research in Asynchronous Circuits and Systems
A Low-Latency FIFO for Mixed-Clock Systems
WVLSI '00 Proceedings of the IEEE Computer Society Annual Workshop on VLSI (WVLSI'00)
Globally-asynchronous locally-synchronous systems (performance, reliability, digital)
Globally-asynchronous locally-synchronous systems (performance, reliability, digital)
Proceedings of the conference on Design, automation and test in Europe - Volume 2
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
NoC Synthesis Flow for Customized Domain Specific Multiprocessor Systems-on-Chip
IEEE Transactions on Parallel and Distributed Systems
Speed and voltage selection for GALS systems based on voltage/frequency islands
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
GALS networks on chip: a new solution for asynchronous delay-insensitive links
Proceedings of the conference on Design, automation and test in Europe: Designers' forum
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Incremental run-time application mapping for homogeneous NoCs with multiple voltage levels
CODES+ISSS '07 Proceedings of the 5th IEEE/ACM international conference on Hardware/software codesign and system synthesis
Variation-adaptive feedback control for networks-on-chip with multiple clock domains
Proceedings of the 45th annual Design Automation Conference
System-level mitigation of WID leakage power variability using body-bias islands
CODES+ISSS '08 Proceedings of the 6th IEEE/ACM/IFIP international conference on Hardware/Software codesign and system synthesis
A voltage-frequency island aware energy optimization framework for networks-on-chip
Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design
Autonomous DVFS on Supply Islands for Energy-Constrained NoC Communication
ARCS '09 Proceedings of the 22nd International Conference on Architecture of Computing Systems
Using adaptive routing to compensate for performance heterogeneity
NOCS '09 Proceedings of the 2009 3rd ACM/IEEE International Symposium on Networks-on-Chip
Energy efficient application mapping to NoC processing elements operating at multiple voltage levels
NOCS '09 Proceedings of the 2009 3rd ACM/IEEE International Symposium on Networks-on-Chip
NoC topology synthesis for supporting shutdown of voltage islands in SoCs
Proceedings of the 46th Annual Design Automation Conference
Design and management of voltage-frequency island partitioned networks-on-chip
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Multiple clock and voltage domains for chip multi processors
Proceedings of the 42nd Annual IEEE/ACM International Symposium on Microarchitecture
Hierarchical agent monitoring design approach towards self-aware parallel systems-on-chip
ACM Transactions on Embedded Computing Systems (TECS)
Leakage-saving opportunities in mesh-based massive multi-core architectures
ACM SIGARCH Computer Architecture News
Proceedings of the 2010 ACM Symposium on Applied Computing
Improving the Performance of GALS-Based NoCs in the Presence of Process Variation
NOCS '10 Proceedings of the 2010 Fourth ACM/IEEE International Symposium on Networks-on-Chip
IEEE Transactions on Circuits and Systems II: Express Briefs
Network on chip design and optimization using specialized influence models
Proceedings of the 47th Design Automation Conference
Energy efficient mapping and voltage islanding for regular NoC under design constraints
International Journal of High Performance Systems Architecture
Custom feedback control: enabling truly scalable on-chip power management for MPSoCs
Proceedings of the 16th ACM/IEEE international symposium on Low power electronics and design
Power efficient voltage islanding for Systems-on-Chip from a floorplanning perspective
Proceedings of the Conference on Design, Automation and Test in Europe
Design space exploration of a mesochronous link for cost-effective and flexible GALS NOCs
Proceedings of the Conference on Design, Automation and Test in Europe
State observer controller design for packets flow control in networks-on-chip
The Journal of Supercomputing
Characterizing the impact of process variation on 45 nm NoC-based CMPs
Journal of Parallel and Distributed Computing
VISION: a framework for voltage island aware synthesis of interconnection networks-on-chip
Proceedings of the 21st edition of the great lakes symposium on Great lakes symposium on VLSI
Economic learning for thermal-aware power budgeting in many-core architectures
CODES+ISSS '11 Proceedings of the seventh IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
Clustering-based simultaneous task and voltage scheduling for NoC systems
Proceedings of the International Conference on Computer-Aided Design
Proceedings of the ACM/SIGDA international symposium on Field Programmable Gate Arrays
Voltage island-driven power optimization for application specific network-on-chip design
Proceedings of the great lakes symposium on VLSI
Integration, the VLSI Journal
PEPON: performance-aware hierarchical power budgeting for NoC based multicores
Proceedings of the 21st international conference on Parallel architectures and compilation techniques
Journal of Computer and System Sciences
System-level leakage variability mitigation for MPSoC platforms using body-bias islands
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Architecturally homogeneous power-performance heterogeneous multicore systems
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Journal of Systems Architecture: the EUROMICRO Journal
Dynamic Power and Thermal Management of NoC-Based Heterogeneous MPSoCs
ACM Transactions on Reconfigurable Technology and Systems (TRETS)
A generic FPGA prototype for on-chip systems with network-on-chip communication infrastructure
Computers and Electrical Engineering
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Due to high levels of integration and complexity, the design of multi-core SoCs has become increasingly challenging. In particular, energy consumption and distributing a single global clock signal throughout a chip have become major design bottlenecks. To deal with these issues, a globally asynchronous, locally synchronous (GALS) design is considered for achieving low power consumption and modular design. Such a design style fits nicely with the concept of voltage-frequency islands (VFIs) which has been recently introduced for achieving fine-grain system-level power management. This paper proposes a design methodology for partitioning an NoC architecture into multiple VFIs and assigning supply and threshold voltage levels to each VFI. Simulation results show about 40% savings for a real video application and demonstrate the effectiveness of our approach in reducing the overall system energy consumption. The results and functional correctness are validated using an FPGA prototype for an NoC with multiple VFIs.