PEPON: performance-aware hierarchical power budgeting for NoC based multicores

Authors:
Akbar Sharifi;Asit K. Mishra;Shekhar Srikantaiah;Mahmut Kandemir;Chita R. Das
Affiliations:
The Pennsylvania State University, University Park, PA, USA;The Pennsylvania State University, University Park, PA, USA;The Pennsylvania State University, University Park, PA, USA;The Pennsylvania State University, University Park, PA, USA;The Pennsylvania State University, University Park, PA, USA
Venue:
Proceedings of the 21st international conference on Parallel architectures and compilation techniques
Year:
2012

Citing 28
Cited 0

Wattch: a framework for architectural-level power analysis and optimizations

Proceedings of the 27th annual international symposium on Computer architecture
Design issues for dynamic voltage scaling

ISLPED '00 Proceedings of the 2000 international symposium on Low power electronics and design
Memory hierarchy reconfiguration for energy and performance in general-purpose processor architectures

Proceedings of the 33rd annual ACM/IEEE international symposium on Microarchitecture
Computer Networking: A Top-Down Approach Featuring the Internet

Computer Networking: A Top-Down Approach Featuring the Internet
Low power system scheduling and synthesis

Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design
Simics: A Full System Simulation Platform

Computer
Integrating Adaptive On-Chip Storage Structures for Reduced Dynamic Power

Proceedings of the 2002 International Conference on Parallel Architectures and Compilation Techniques
Orion: a power-performance simulator for interconnection networks

Proceedings of the 35th annual ACM/IEEE international symposium on Microarchitecture
Feedback Control of Computing Systems

Feedback Control of Computing Systems
Formal online methods for voltage/frequency control in multiple clock domain microprocessors

ASPLOS XI Proceedings of the 11th international conference on Architectural support for programming languages and operating systems
Heat-and-run: leveraging SMT and CMP to manage power density through the operating system

ASPLOS XI Proceedings of the 11th international conference on Architectural support for programming languages and operating systems
On the Limits of Leakage Power Reduction in Caches

HPCA '05 Proceedings of the 11th International Symposium on High-Performance Computer Architecture
Coordinated, distributed, formal energy management of chip multiprocessors

ISLPED '05 Proceedings of the 2005 international symposium on Low power electronics and design
Maximizing CMP Throughput with Mediocre Cores

Proceedings of the 14th International Conference on Parallel Architectures and Compilation Techniques
Techniques for Multicore Thermal Management: Classification and New Exploration

Proceedings of the 33rd annual international symposium on Computer Architecture
An Analysis of Efficient Multi-Core Global Power Management Policies: Maximizing Performance for a Given Power Budget

Proceedings of the 39th Annual IEEE/ACM International Symposium on Microarchitecture
Utility-Based Cache Partitioning: A Low-Overhead, High-Performance, Runtime Mechanism to Partition Shared Caches

Proceedings of the 39th Annual IEEE/ACM International Symposium on Microarchitecture
Voltage-frequency island partitioning for GALS-based networks-on-chip

Proceedings of the 44th annual Design Automation Conference
Evaluating design tradeoffs in on-chip power management for CMPs

ISLPED '07 Proceedings of the 2007 international symposium on Low power electronics and design
A 5-GHz Mesh Interconnect for a Teraflops Processor

IEEE Micro
Power/Performance/Thermal Design-Space Exploration for Multicore Architectures

IEEE Transactions on Parallel and Distributed Systems
Multi-optimization power management for chip multiprocessors

Proceedings of the 17th international conference on Parallel architectures and compilation techniques
Reconfigurable energy efficient near threshold cache architectures

Proceedings of the 41st annual IEEE/ACM International Symposium on Microarchitecture
Temperature-constrained power control for chip multiprocessors with online model estimation

Proceedings of the 36th annual international symposium on Computer architecture
SHIP: Scalable Hierarchical Power Control for Large-Scale Data Centers

PACT '09 Proceedings of the 2009 18th International Conference on Parallel Architectures and Compilation Techniques
CPM in CMPs: Coordinated Power Management in Chip-Multiprocessors

Proceedings of the 2010 ACM/IEEE International Conference for High Performance Computing, Networking, Storage and Analysis
Scalable power control for many-core architectures running multi-threaded applications

Proceedings of the 38th annual international symposium on Computer architecture
Migration, assignment, and scheduling of jobs in virtualized environment

HotCloud'11 Proceedings of the 3rd USENIX conference on Hot topics in cloud computing

Quantified Score

Hi-index	0.00

Visualization

Abstract

Targeting NoC based multicores, we propose a two-level power budget distribution mechanism, called PEPON, where the first level distributes the overall power budget of the multicore system among various types of on-chip resources like the cores, caches, and NoC, and the second level determines the allocation of power to individual instances of each type of resource. Both these distributions are oriented towards maximizing workload performance without exceeding the specified power budget. Extensive experimental evaluations of the proposed power distribution scheme using a full system simulation and detailed power models emphasize the importance of power budget partitioning at both levels. Specifically, our results show that the proposed scheme can provide up to 29% performance improvement as compared to no power budgeting, and performs 13% better than a competing scheme, under the same chip-wide power cap.