Digital integrated circuits: a design perspective
Digital integrated circuits: a design perspective
Managing power and performance for System-on-Chip designs using Voltage Islands
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
A Low-Latency FIFO for Mixed-Clock Systems
WVLSI '00 Proceedings of the IEEE Computer Society Annual Workshop on VLSI (WVLSI'00)
Principles and Practices of Interconnection Networks
Principles and Practices of Interconnection Networks
Mapping and configuration methods for multi-use-case networks on chips
ASP-DAC '06 Proceedings of the 2006 Asia and South Pacific Design Automation Conference
A low complexity heuristic for design of custom network-on-chip architectures
Proceedings of the conference on Design, automation and test in Europe: Proceedings
Linear-programming-based techniques for synthesis of network-on-chip architectures
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Hardware based frequency/voltage control of voltage frequency island systems
CODES+ISSS '06 Proceedings of the 4th international conference on Hardware/software codesign and system synthesis
Designing application-specific networks on chips with floorplan information
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
Voltage-frequency island partitioning for GALS-based networks-on-chip
Proceedings of the 44th annual Design Automation Conference
Energy-aware synthesis of networks-on-chip implemented with voltage islands
Proceedings of the 44th annual Design Automation Conference
A voltage-frequency island aware energy optimization framework for networks-on-chip
Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design
NoC topology synthesis for supporting shutdown of voltage islands in SoCs
Proceedings of the 46th Annual Design Automation Conference
Proceedings of the 2010 ACM Symposium on Applied Computing
ORION 2.0: a fast and accurate NoC power and area model for early-stage design space exploration
Proceedings of the Conference on Design, Automation and Test in Europe
Application-specific 3D Network-on-Chip design using simulated allocation
Proceedings of the 2010 Asia and South Pacific Design Automation Conference
"It's a small world after all": noc performance optimization via long-range link insertion
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Energy- and performance-aware mapping for regular NoC architectures
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Energy- and Performance-Aware Incremental Mapping for Networks on Chip With Multiple Voltage Levels
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Voltage island-driven power optimization for application specific network-on-chip design
Proceedings of the great lakes symposium on VLSI
Utilizing voltage-frequency islands in C-to-RTL synthesis for streaming applications
Proceedings of the Conference on Design, Automation and Test in Europe
A generic FPGA prototype for on-chip systems with network-on-chip communication infrastructure
Computers and Electrical Engineering
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High power dissipation has today become one of the major challenges in chip multiprocessor (CMP) design. Designers in recent years have proposed several techniques to alleviate the power challenge, one of which is the use of voltage islands (VIs) that can help reduce both switching and standby components of power. The use of VIs allows groups of cores to be powered by the same supply source and permits operating different portions of the chip at different voltage levels in order to optimize the overall chip power consumption. However, the problems of VI creation, core to VI mapping, and VI-aware network on chip (NoC) design to satisfy application performance constraints are non-trivial and will only get harder as the number of cores in CMPs increase into the hundreds. In this paper, we propose a novel framework (VISION) for automating the synthesis of regular networks on chip (NoC) with VIs, to satisfy application performance while minimizing chip power dissipation. Our proposed framework uses a set of novel algorithms and heuristics to generate solutions that reduce network traffic by up to 60% and power dissipation by up to 11%, compared to the best known prior work that also solves the same problem.