Deadlock-Free Message Routing in Multiprocessor Interconnection Networks
IEEE Transactions on Computers
Floorplan sizing by linear programming approximation
Proceedings of the 37th Annual Design Automation Conference
Route packets, not wires: on-chip inteconnection networks
Proceedings of the 38th annual Design Automation Conference
VISI Physical Design Automation: Theory and Practice
VISI Physical Design Automation: Theory and Practice
A linear-time heuristic for improving network partitions
DAC '82 Proceedings of the 19th Design Automation Conference
Efficient Synthesis of Networks On Chip
ICCD '03 Proceedings of the 21st International Conference on Computer Design
Bandwidth-Constrained Mapping of Cores onto NoC Architectures
Proceedings of the conference on Design, automation and test in Europe - Volume 2
×pipesCompiler: A Tool for Instantiating Application Specific Networks on Chip
Proceedings of the conference on Design, automation and test in Europe - Volume 2
Linear Programming based Techniques for Synthesis of Network-on-Chip Architectures
ICCD '04 Proceedings of the IEEE International Conference on Computer Design
ISIS: A Genetic Algorithm Based Technique for Custom On-Chip Interconnection Network Synthesis
VLSID '05 Proceedings of the 18th International Conference on VLSI Design held jointly with 4th International Conference on Embedded Systems Design
Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
A technique for low energy mapping and routing in network-on-chip architectures
ISLPED '05 Proceedings of the 2005 international symposium on Low power electronics and design
Energy-aware mapping for tile-based NoC architectures under performance constraints
ASP-DAC '03 Proceedings of the 2003 Asia and South Pacific Design Automation Conference
Mapping and physical planning of networks-on-chip architectures with quality-of-service guarantees
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
SAGA: synthesis technique for guaranteed throughput NoC architectures
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
Linear-programming-based techniques for synthesis of network-on-chip architectures
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A linear programming-based algorithm for floorplanning in VLSI design
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Elastic Flow in an Application Specific Network-on-Chip
Electronic Notes in Theoretical Computer Science (ENTCS)
NoCOUT: NoC topology generation with mixed packet-switched and point-to-point networks
Proceedings of the 2008 Asia and South Pacific Design Automation Conference
Mixed integer linear programming-based optimal topology synthesis of cascaded crossbar switches
Proceedings of the 2008 Asia and South Pacific Design Automation Conference
NOCS '09 Proceedings of the 2009 3rd ACM/IEEE International Symposium on Networks-on-Chip
Outstanding research problems in NoC design: system, microarchitecture, and circuit perspectives
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Design Trade-offs in Customized On-chip Crossbar Schedulers
Journal of Signal Processing Systems
Systematic customization of on-chip crossbar interconnects
ARC'07 Proceedings of the 3rd international conference on Reconfigurable computing: architectures, tools and applications
Virtual point-to-point connections for NoCs
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems - Special issue on the 2009 ACM/IEEE international symposium on networks-on-chip
A method to remove deadlocks in networks-on-chips with wormhole flow control
Proceedings of the Conference on Design, Automation and Test in Europe
Workload characterization and its impact on multicore platform design
CODES/ISSS '10 Proceedings of the eighth IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
3D network-on-chip architectures using homogeneous meshes and heterogeneous floorplans
International Journal of Reconfigurable Computing - Special issue on selected papers from ReconFig 2009 International conference on reconfigurable computing and FPGAs (ReconFig 2009)
VISION: a framework for voltage island aware synthesis of interconnection networks-on-chip
Proceedings of the 21st edition of the great lakes symposium on Great lakes symposium on VLSI
Application-aware deadlock-free oblivious routing based on extended turn-model
Proceedings of the International Conference on Computer-Aided Design
Integration, the VLSI Journal
Journal of Computer and System Sciences
Physical-aware system-level design for tiled hierarchical chip multiprocessors
Proceedings of the 2013 ACM international symposium on International symposium on physical design
A NOC closed-loop performance monitor and adapter
Microprocessors & Microsystems
Journal of Systems Architecture: the EUROMICRO Journal
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Network-on-Chip (NoC) has been proposed to replace traditional bus based architectures to address the global communication challenges in nanoscale technologies. In future SoC architectures, minimizing power consumption will continue to be an important design goal. In this paper, we present a novel heuristic technique consisting of system-level physical design, and interconnection network generation that generates custom low power NoC architectures for application specific SoC. We demonstrate the quality of the solutions produced by our technique by experimentation with many benchmarks. Our technique has a low computational complexity, and consumes only 1.25 times the power consumption, and 0.85 times the number of router resources compared to an optimal MILP based technique [1] whose computational complexity is not bounded.