Deadlock-Free Message Routing in Multiprocessor Interconnection Networks
IEEE Transactions on Computers
The turn model for adaptive routing
ISCA '92 Proceedings of the 19th annual international symposium on Computer architecture
Smart Memories: a modular reconfigurable architecture
Proceedings of the 27th annual international symposium on Computer architecture
The Odd-Even Turn Model for Adaptive Routing
IEEE Transactions on Parallel and Distributed Systems
Interconnection Networks: An Engineering Approach
Interconnection Networks: An Engineering Approach
Deadlock-Free Adaptive Routing in Multicomputer Networks Using Virtual Channels
IEEE Transactions on Parallel and Distributed Systems
A Necessary and Sufficient Condition for Deadlock-Free Adaptive Routing in Wormhole Networks
IEEE Transactions on Parallel and Distributed Systems
Uniform Crossover in Genetic Algorithms
Proceedings of the 3rd International Conference on Genetic Algorithms
A large scale, homogeneous, fully distributed parallel machine, I
ISCA '77 Proceedings of the 4th annual symposium on Computer architecture
Approximation algorithms for disjoint paths problems
Approximation algorithms for disjoint paths problems
Bandwidth-Constrained Mapping of Cores onto NoC Architectures
Proceedings of the conference on Design, automation and test in Europe - Volume 2
Principles and Practices of Interconnection Networks
Principles and Practices of Interconnection Networks
A low complexity heuristic for design of custom network-on-chip architectures
Proceedings of the conference on Design, automation and test in Europe: Proceedings
ISCA '08 Proceedings of the 35th Annual International Symposium on Computer Architecture
ISCA '08 Proceedings of the 35th Annual International Symposium on Computer Architecture
Self-adaptive mutation rates in genetic algorithm for inverse design of cellular automata
Proceedings of the 10th annual conference on Genetic and evolutionary computation
Hardwired Networks on Chip in FPGAs to Unify Functional and Con?guration Interconnects
NOCS '08 Proceedings of the Second ACM/IEEE International Symposium on Networks-on-Chip
Application Specific Routing Algorithms for Networks on Chip
IEEE Transactions on Parallel and Distributed Systems
Application-aware deadlock-free oblivious routing
Proceedings of the 36th annual international symposium on Computer architecture
Static virtual channel allocation in oblivious routing
NOCS '09 Proceedings of the 2009 3rd ACM/IEEE International Symposium on Networks-on-Chip
Proceedings of the 47th Design Automation Conference
Designing heterogeneous embedded network-on-chip platforms with users in mind
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
A method to remove deadlocks in networks-on-chips with wormhole flow control
Proceedings of the Conference on Design, Automation and Test in Europe
A highly resilient routing algorithm for fault-tolerant NoCs
Proceedings of the Conference on Design, Automation and Test in Europe
Segment-based routing: an efficient fault-tolerant routing algorithm for meshes and Tori
IPDPS'06 Proceedings of the 20th international conference on Parallel and distributed processing
Energy- and Performance-Aware Incremental Mapping for Networks on Chip With Multiple Voltage Levels
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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Programmable hardware is gaining popularity as it can keep pace with growing performance demand in tight power budget, design and test cost, and serious reliability concerns of future multiprocessor embedded systems. Compatible with this trend, Network-on-Chip, as a potential bottleneck of future multi-cores, should also support programmability. Here, we address this issue in design and implementation of routing algorithm for two-dimensional mesh. To this end, we allocate paths based on input traffic pattern and in parallel with customizing routing restriction for deadlock freedom. To achieve this, we propose extended turn model (ETM), a novel parametric deadlock-free routing for 2D meshes that generalize prior turn-based routing methods (e.g., odd-even) with great degree of freedoms. This model facilitates design of Mixed-Integer Linear Programming (MILP) approach, which considers channel dependency turns as independent variables and decides for both path allocation and routing restriction. We solve this problem by genetic algorithm and evaluate it using simulation experiments. Results reveal that application-aware ETM-based path allocation outperforms prior turn-based approaches under synthetic and real traffic loads.