The happy marriage of architecture and application in next-generation reconfigurable systems
Proceedings of the 1st conference on Computing frontiers
Chip multi-processor generator
Proceedings of the 44th annual Design Automation Conference
Application-aware deadlock-free oblivious routing based on extended turn-model
Proceedings of the International Conference on Computer-Aided Design
| Hi-index | 4.10 |
To remain competitive, system-on-chip designers must keep pace with silicon technology's rapid evolution.One approach to speeding development of megagate SoCs uses multiple micro-processor cores to perform much of the processing currently relegated to register-transfer-level (RTL) techniques. Although general-purpose embedded processors handle many tasks, they often lack the bandwidth needed to perform particularly complex jobs, such as audio and video processing. Hence the historic rise of RTL use in SoC design.Developers can configure a new class of processor--extensible microprocessor cores--to bring the required amount and type of processing bandwidth to bear on many embedded tasks. Because these processors employ firmware instead of RTL-defined hardware for their control algorithm, designers can develop and verify processor-based task engines for many embedded SoC tasks more quickly and easily.