Dynamically-Allocated Multi-Queue Buffers for VLSI Communication Switches
IEEE Transactions on Computers
Leakage power modeling and optimization in interconnection networks
Proceedings of the 2003 international symposium on Low power electronics and design
SoCIN: A Parametric and Scalable Network-on-Chip
SBCCI '03 Proceedings of the 16th symposium on Integrated circuits and systems design
xpipes: a Latency Insensitive Parameterized Network-on-chip Architecture For Multi-Processor SoCs
ICCD '03 Proceedings of the 21st International Conference on Computer Design
NoC Synthesis Flow for Customized Domain Specific Multiprocessor Systems-on-Chip
IEEE Transactions on Parallel and Distributed Systems
Towards on-chip fault-tolerant communication
ASP-DAC '03 Proceedings of the 2003 Asia and South Pacific Design Automation Conference
A low complexity heuristic for design of custom network-on-chip architectures
Proceedings of the conference on Design, automation and test in Europe: Proceedings
ViChaR: A Dynamic Virtual Channel Regulator for Network-on-Chip Routers
Proceedings of the 39th Annual IEEE/ACM International Symposium on Microarchitecture
Research on Node Coding and Routing Algorithm for Network on Chip
CCCM '08 Proceedings of the 2008 ISECS International Colloquium on Computing, Communication, Control, and Management - Volume 01
ROAdNoC: runtime observability for an adaptive network on chip architecture
Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design
Reliability aware NoC router architecture using input channel buffer sharing
Proceedings of the 19th ACM Great Lakes symposium on VLSI
NoC Power Optimization Using a Reconfigurable Router
ISVLSI '09 Proceedings of the 2009 IEEE Computer Society Annual Symposium on VLSI
BiNoC: A bidirectional NoC architecture with dynamic self-reconfigurable channel
NOCS '09 Proceedings of the 2009 3rd ACM/IEEE International Symposium on Networks-on-Chip
International Journal of High Performance Systems Architecture
System-Level Buffer Allocation for Application-Specific Networks-on-Chip Router Design
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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In a NoC, the amount of buffers allocated to each communication channel has a significant impact on performance and power consumption. Moreover, since there will be changes in the application communication pattern, or even because a new application is loaded in a SoC, a design based on the worst case scenario will probably either oversize buffers, with obvious power implications, or the performance will be compromised, since not enough buffers will be available. A runtime mechanism is required to automatically adapt the buffer size as a function of the communication pattern. This paper proposes a control mechanism to resize the buffer of an adaptive router. The runtime mechanism is able to monitor the traffic behavior and to control, for each channel, the required buffer size of the adaptive router. Besides, as the complexity of designs increase and technologies scale down, devices are subject to new types of malfunctions and failures. Network-on-chip routers are responsible to ensure the proper communication of on-chip cores, and the buffers present in the router channels are crucial to ensure the communication performance. This way, a technique to isolate faulty buffers is also presented. Experimental results using the proposed architecture have shown that, in the absence of faults, the latency has been decreased by 80%, and throughput has been increased by 45%, in the worst case. In the presence of faults, the proposed architecture was able to sustain the same performance of the equivalent homogeneous router, but with up to 25% power savings.